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Implementation of Trinary/Quaternary Addition using Multivalue Logic Digital Circuit
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 118 - Number 4 |
| Year of Publication: 2015 |
| Authors: Braj Kishor, Anand Kumar Singh, Sachin Bandewar |
10.5120/20735-3114
|
Braj Kishor, Anand Kumar Singh, Sachin Bandewar . Implementation of Trinary/Quaternary Addition using Multivalue Logic Digital Circuit. International Journal of Computer Applications. 118, 4 ( May 2015), 22-25. DOI=10.5120/20735-3114
Abstract
Objective of multivalve logic design is to reduce number of gates needed and also to reduce interconnect path length. Interconnect path consist of the largest number of gates from input to output. The reason of these two objectives is that they will give extremely good properties when implemented in VLSI. Reducing number of gates will reduce the chip area, and minimizing interconnect path length will give opportunity to use highest clock frequency. In this paper quaternary to binary and binary to quaternary converter are designed. We can design the multivalve logic to binary converter which is use for conversion of ternary-valued input 0,1,2 and quaternary-valued input 0,1,2,3 into corresponding binary-valued output 0,1. The physical design of the circuits is simulated and tested with MICROWIND layout design tool in 50nm technology. The conversion method is simple and compatible with the present CMOS process. The circuits could be embedded in digital CMOS VLSI design architectures.
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