The week's pick
Reseach Article
Implementation of Trinary/Quaternary Addition using Multivalue Logic Digital Circuit
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 118 - Number 4 |
| Year of Publication: 2015 |
| Authors: Braj Kishor, Anand Kumar Singh, Sachin Bandewar |
10.5120/20735-3114
|
Braj Kishor, Anand Kumar Singh, Sachin Bandewar . Implementation of Trinary/Quaternary Addition using Multivalue Logic Digital Circuit. International Journal of Computer Applications. 118, 4 ( May 2015), 22-25. DOI=10.5120/20735-3114
Abstract
Objective of multivalve logic design is to reduce number of gates needed and also to reduce interconnect path length. Interconnect path consist of the largest number of gates from input to output. The reason of these two objectives is that they will give extremely good properties when implemented in VLSI. Reducing number of gates will reduce the chip area, and minimizing interconnect path length will give opportunity to use highest clock frequency. In this paper quaternary to binary and binary to quaternary converter are designed. We can design the multivalve logic to binary converter which is use for conversion of ternary-valued input 0,1,2 and quaternary-valued input 0,1,2,3 into corresponding binary-valued output 0,1. The physical design of the circuits is simulated and tested with MICROWIND layout design tool in 50nm technology. The conversion method is simple and compatible with the present CMOS process. The circuits could be embedded in digital CMOS VLSI design architectures.
References
- Milton Ernesto Romero, Evandro Mazina Martins, Ricardo Ribeiro dos Santos, and Mario Enrique Duarte Gonzalez "Universal Set of CMOS Gates for the Synthesis of Multiple Valued Logic Digital Circuits" IEEE Transactions On Circuits And Systems—I: Regular Papers, Vol. 61, No. 3, March 2014 pp no 736-749. .
- Fatma Sarica and Avni Morgu "Basic Circuits for Multi-Valued Sequential Logic" International Conference on Electrical and Electronics Engineering ELECO dec 2011 pp no. 56-58.
- Vasundara Patel, k s gurumurthy "Arithmatic Operation in Multivalve Logic" International journal of VLSI design and communication system (VLSICS) Vol 1 no 1 March 2010 pp no. 21-32.
- Tanay Chattopadhyay and Tamal Sarkar "Logical Design of Quaternary Signed Digit Conversion Circuit and its Effectuation using Operational Amplifier" International Journal of Power Systems and Integrated Circuits, Vol. 2, No. 3, December 2012 pp no. 7-12.
- V. T. Gaikwad & P R. Deshmukh "Design Of Cmos Ternary Logic Gates" International Journal of Electrical and Electronics Engineering Research (IJEEER) Vol. 4, Issue 4, Aug 2014.
- Mahsa Dornajafi, Steve E. Watkins, Benjamin Cooper, and M. Ryan Bales "Performance of a Quaternary Logic Design" IEEE International Conference in year 2008.
- Jinghang Liang, Linbin Chen, Jie Han, and Fabrizio Lombardi "Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs" IEEE Transactions On Nanotechnology, Vol. 13, No. 4, July 2014 pp no. 695-708.
- Diogo Brito, Student Member, Taimur G. Rabuske, Jorge R. Fernandes, Paulo Flores, Senior Member, and José Monteiro "Quaternary Logic Lookup Table in Standard CMOS" IEEE Transactions On Very Large Scale Integration (Vlsi) Systems year dec 2014pp no. 1-11.
- Sheng Lin, Student Member, Yong-Bin Kim, Senior Member, and Fabrizio Lombardi "CNTFET-Based Design of Ternary Logic Gates and Arithmetic Circuits" IEEE Transactions On Nanotechnology, Vol. 10, No. 2, March 2011 pp no. 217-225.
Index Terms
Keywords