The week's pick
Reseach Article
Illustrative Comparison of MCML and CMOS Design Techniques using Tanner EDA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 118 - Number 4 |
| Year of Publication: 2015 |
| Authors: Keerti Vyas, Ginni Jain, Vijendra K. Maurya, Rajeev Mathur |
10.5120/20734-3110
|
Keerti Vyas, Ginni Jain, Vijendra K. Maurya, Rajeev Mathur . Illustrative Comparison of MCML and CMOS Design Techniques using Tanner EDA. International Journal of Computer Applications. 118, 4 ( May 2015), 18-21. DOI=10.5120/20734-3110
Abstract
In this paper, a comparison is done between MOS Current Mode Logic (MCML) and Complementary metal Oxide Semiconductor (CMOS) circuits operating in low power application. It is found that MCML logic circuits exhibit a decrease in delay and so decrease in overall power delay product compared with CMOS circuits. The tested inverter are optimized for low power and high-speed operation, according to the simulation of the circuits for lower voltage. This simulation is done using Tanner EDA. From the results shown it is seen that the MCML logic circuits reveal high efficiency and good performance at low power and high speeds which makes them to be more capable for application in the integrated circuits with high density.
References
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- Lisha Li, Sripriya Raghavendran, and Donald T. Comer," CMOS Current Mode LogicGates for High-Speed "Department of Electrical and Computer Engineering Brigham Young University, Oct, 2005
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- K. Gupta, N. Pandey and M. Gupta "A Novel Active Shunt-Peaked MCML-based High Speed Four-Bit Ripple-Carry Adder" Int'l Conf. on Computer & Communication Technology, IEEE 2010.
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