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Performance Analysis of Verilog Directed Testbench vs Constrained Random SystemVerilog Testbench

by Deepika Ahlawat, Neeraj Kr. Shukla
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 118 - Number 22
Year of Publication: 2015
Authors: Deepika Ahlawat, Neeraj Kr. Shukla
10.5120/20874-3612

Deepika Ahlawat, Neeraj Kr. Shukla . Performance Analysis of Verilog Directed Testbench vs Constrained Random SystemVerilog Testbench. International Journal of Computer Applications. 118, 22 ( May 2015), 1-7. DOI=10.5120/20874-3612

@article{ 10.5120/20874-3612,
author = { Deepika Ahlawat, Neeraj Kr. Shukla },
title = { Performance Analysis of Verilog Directed Testbench vs Constrained Random SystemVerilog Testbench },
journal = { International Journal of Computer Applications },
issue_date = { May 2015 },
volume = { 118 },
number = { 22 },
month = { May },
year = { 2015 },
issn = { 0975-8887 },
pages = { 1-7 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume118/number22/20874-3612/ },
doi = { 10.5120/20874-3612 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:02:45.839151+05:30
%A Deepika Ahlawat
%A Neeraj Kr. Shukla
%T Performance Analysis of Verilog Directed Testbench vs Constrained Random SystemVerilog Testbench
%J International Journal of Computer Applications
%@ 0975-8887
%V 118
%N 22
%P 1-7
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

SystemVerilog is the emerging language of choice for modern day VLSI design and verification. SystemVerilog (SV) brings a advanced level of abstraction to the system being modeled. The advanced constructs it utilizes its OOP capability make it stand apart from other verification languages. In this paper we will be analyzing the performance of SV testbench over Verilog testbench, using well defined comparison parameters tested against an actual IP design block, along with other features of the SV language.

References
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  2. Stuart Sutherland, "Don't Forget the Little Things That Can Make Verification Easier," Verification Horizons, Mentor Graphics
  3. SystemVerilog 3. 1a, Language Reference Manual
  4. Welp Tobias, Kitchen Nathan, and Kuehlmann Andreas, "Hardware Acceleration for Constraint Solving for Random Simulation,"IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 31, No. 5, May 2012
  5. SudhishNaveen, BR Raghavendra, YagainHarish, "An Efficient Method for Using Transaction Level Assertions in a Class Based Verification Environment," International Symposium on Electronic System Design,pp. 72-76, 2011
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Index Terms

Computer Science
Information Sciences

Keywords

Assertions Coverage Environment Mailbox Randomization SystemVerilog Threads Transactions Testbench

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