CFP last date
20 December 2024
Reseach Article

A Simulation Algorithm for Prediction of Random Variations in Digital Circuits

by Hamid Reza Shokuhfar, Daryoosh Dideban, Negin Moezi, Hamed Jooypa
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 118 - Number 18
Year of Publication: 2015
Authors: Hamid Reza Shokuhfar, Daryoosh Dideban, Negin Moezi, Hamed Jooypa
10.5120/20849-3546

Hamid Reza Shokuhfar, Daryoosh Dideban, Negin Moezi, Hamed Jooypa . A Simulation Algorithm for Prediction of Random Variations in Digital Circuits. International Journal of Computer Applications. 118, 18 ( May 2015), 37-40. DOI=10.5120/20849-3546

@article{ 10.5120/20849-3546,
author = { Hamid Reza Shokuhfar, Daryoosh Dideban, Negin Moezi, Hamed Jooypa },
title = { A Simulation Algorithm for Prediction of Random Variations in Digital Circuits },
journal = { International Journal of Computer Applications },
issue_date = { May 2015 },
volume = { 118 },
number = { 18 },
month = { May },
year = { 2015 },
issn = { 0975-8887 },
pages = { 37-40 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume118/number18/20849-3546/ },
doi = { 10.5120/20849-3546 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:02:06.408193+05:30
%A Hamid Reza Shokuhfar
%A Daryoosh Dideban
%A Negin Moezi
%A Hamed Jooypa
%T A Simulation Algorithm for Prediction of Random Variations in Digital Circuits
%J International Journal of Computer Applications
%@ 0975-8887
%V 118
%N 18
%P 37-40
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

A novel simulation algorithm capable of capturing statistical variability manifests in digital design is proposed. The only estimations for the algorithm inputs are the standard deviations of channel length and the gate voltage. Implementing the algorithm for the simulation of propagation delay times of the basic digital building blocks such as inverter, NAND2 and NOR2 circuits gives errors less than 7% against the most accurate results obtained from 'atomistic' HSPICE simulations.

References
  1. F. Hong, B. Cheng, S. Roy and D. Cumming, "An Analytical Mismatch Model for on coms Device under the Impact of Intrinsic Device Variability", IEEE ISCAS May, pp. 2257-2260, 2011.
  2. G. Cijan, T. Tuma and A. Burmen, "Modeling and simulation of MOS transistor mismatch", International Conference on Proc. 6th Eurosim, 2007.
  3. V. Wason, J. An, Jung-Suk Goo, Zhi-Yuan Wu, Qiang Chen, C. Thuruthiyil, R. Topaloglu, P. Chiney and A. Icel, "Statistical Compact Modeling and Si Verification Methodology", International Conference onSolid-State and Integrated Circuit Technology, pp. 1198 – 1201, 2006.
  4. K. Bult and A. Buchwald, "An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm", IEEE Journal of Solid-State Circuits, Vol. 32, pp. 1887-1895, 1997.
  5. J. B. Shyu et al. , "Random errors in MOS capacitors", IEEE Journal of Solid- State Circuits, Vol. 17, No. 6, pp. 948–955, 1982.
  6. J. B. Shyu et al. , "Random error effects in matched MOS capacitors and current sources", IEEE Journal of Solid-State Circuits, vol. 19, pp. 1070-1076, 1984.
  7. M. Pelgrom, A. Duinmaijer and A. Welbers, "Matching properties of MOS transistors", IEEE Journal of Solid-State Circuits, Vol. 24, No. 6, pp. 1433-1989, 1989.
  8. T. Sakurai and A. R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," Solid-State Circuits, IEEE Journal of, vol. 25, pp. 584-594, 1990.
  9. M. M. Mansour and A. Mehrotra, "Modified Sakurai-Newton current model and its applications to CMOS digital circuit design," in VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on, 2003, pp. 62-69.
  10. N. Chandra, A. Kumar Yati, and A. B. Bhattacharyya, "Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design," VLSI Design, 2009 22nd International Conference on, pp. 247-252, 5-9 Jan. 2009 2009.
  11. S. Gummalla, A. R. Subramaniam, C. Yu, and C. Chakrabarti, "An analytical approach to efficient circuit variability analysis in scaled CMOS design," in Quality Electronic Design (ISQED), 2012 13th International Symposium on, 2012, pp. 641-647.
  12. P. Liu, Y. -B. Kim, and Y. J. Lee, "An accurate analytical propagation delay model of nano CMOS circuits," in IEEE International SoC Design Conference (ISOCC), 2007, pp. 200-203.
  13. R. Keyes, "Effect of randomness in the distribution of impurity ions on FET thresholds in integrated electronics", IEEE Journal of Solid-State Circuit, Vol. 10, No. 4, pp. 245-247, 1975.
  14. A. Asenov, S. Kaya, and A. Brown, "Intrinsic parameter fluctuations in decananometer MOSFETS introduced by gate line edge roughness", IEEE Transactions on Electron Devices, Vol. 50, No. 5, pp. 1254-1260, 2003.
  15. Asenov, M. Jaraiz, S. Roy, G. Roy, et al. , "Integrated Atomistic. Process and Device Simulation of Decananometre MOSFETs", Proc. SISPAD2002, pp. 87-90, 2002.
  16. Cheng, et al. "Integrating 'atomistic', intrinsic parameter fluctuations into compact model circuit analysis. " European Solid-State Device Research, ESSDERC'03. 33rd Conference on. IEEE, 2003.
Index Terms

Computer Science
Information Sciences

Keywords

Statistical variability Digital design Monte-Carlo simulation statistical modeling nano-CMOS