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Design and Implementation of RNS Reverse Converter using Parallel Prefix Adders
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 117 - Number 6 |
| Year of Publication: 2015 |
| Authors: M.kuttimani Rajalingam, A.muthumanicckam, R.sornalatha |
10.5120/20558-2945
|
M.kuttimani Rajalingam, A.muthumanicckam, R.sornalatha . Design and Implementation of RNS Reverse Converter using Parallel Prefix Adders. International Journal of Computer Applications. 117, 6 ( May 2015), 16-20. DOI=10.5120/20558-2945
Abstract
The implementation of residue number system reverse converters based on well-known regular and modular parallel prefix adders is analyzed. The VLSI implementation results show a significant delay reduction and area × time2 improvements, all this at the cost of higher power consumption, which is the main reason preventing the use of parallel-prefix adders to achieve high-speed reverse converters in recent systems. Hence, to solve the high power consumption problem, novel specific hybrid parallel-prefix based adder components that provide better trade-off between delay and power consumption are herein presented to design reverse converters. We propose Parallel distributed arithmetic convolution technique in Reverse Converter to increase the system performance
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