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Design and Implementation of RNS Reverse Converter using Parallel Prefix Adders

by M.kuttimani Rajalingam, A.muthumanicckam, R.sornalatha
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 117 - Number 6
Year of Publication: 2015
Authors: M.kuttimani Rajalingam, A.muthumanicckam, R.sornalatha
10.5120/20558-2945

M.kuttimani Rajalingam, A.muthumanicckam, R.sornalatha . Design and Implementation of RNS Reverse Converter using Parallel Prefix Adders. International Journal of Computer Applications. 117, 6 ( May 2015), 16-20. DOI=10.5120/20558-2945

@article{ 10.5120/20558-2945,
author = { M.kuttimani Rajalingam, A.muthumanicckam, R.sornalatha },
title = { Design and Implementation of RNS Reverse Converter using Parallel Prefix Adders },
journal = { International Journal of Computer Applications },
issue_date = { May 2015 },
volume = { 117 },
number = { 6 },
month = { May },
year = { 2015 },
issn = { 0975-8887 },
pages = { 16-20 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume117/number6/20558-2945/ },
doi = { 10.5120/20558-2945 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:58:36.509884+05:30
%A M.kuttimani Rajalingam
%A A.muthumanicckam
%A R.sornalatha
%T Design and Implementation of RNS Reverse Converter using Parallel Prefix Adders
%J International Journal of Computer Applications
%@ 0975-8887
%V 117
%N 6
%P 16-20
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The implementation of residue number system reverse converters based on well-known regular and modular parallel prefix adders is analyzed. The VLSI implementation results show a significant delay reduction and area × time2 improvements, all this at the cost of higher power consumption, which is the main reason preventing the use of parallel-prefix adders to achieve high-speed reverse converters in recent systems. Hence, to solve the high power consumption problem, novel specific hybrid parallel-prefix based adder components that provide better trade-off between delay and power consumption are herein presented to design reverse converters. We propose Parallel distributed arithmetic convolution technique in Reverse Converter to increase the system performance

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Index Terms

Computer Science
Information Sciences

Keywords

Digital arithmetic parallel-prefix adder (PPX) residue number system (RNS) parallel distributed arithmetic convolution architecture reverse converter.

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