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Reseach Article

Reconfigurable Stimulus Generator for Receive Beamformer Test-bed

by Khyati R.zalawadia, Neeraj Mishra, Himanshu Shah, U.d.dalal
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 117 - Number 5
Year of Publication: 2015
Authors: Khyati R.zalawadia, Neeraj Mishra, Himanshu Shah, U.d.dalal
10.5120/20548-2922

Khyati R.zalawadia, Neeraj Mishra, Himanshu Shah, U.d.dalal . Reconfigurable Stimulus Generator for Receive Beamformer Test-bed. International Journal of Computer Applications. 117, 5 ( May 2015), 4-9. DOI=10.5120/20548-2922

@article{ 10.5120/20548-2922,
author = { Khyati R.zalawadia, Neeraj Mishra, Himanshu Shah, U.d.dalal },
title = { Reconfigurable Stimulus Generator for Receive Beamformer Test-bed },
journal = { International Journal of Computer Applications },
issue_date = { May 2015 },
volume = { 117 },
number = { 5 },
month = { May },
year = { 2015 },
issn = { 0975-8887 },
pages = { 4-9 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume117/number5/20548-2922/ },
doi = { 10.5120/20548-2922 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T23:00:23.439200+05:30
%A Khyati R.zalawadia
%A Neeraj Mishra
%A Himanshu Shah
%A U.d.dalal
%T Reconfigurable Stimulus Generator for Receive Beamformer Test-bed
%J International Journal of Computer Applications
%@ 0975-8887
%V 117
%N 5
%P 4-9
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Laboratory testing of digital beamforming processor is required to test and optimize the beamformer algorithm, code and hardware before integrating with antenna and testing the beamformer in an anechoic chamber. Development of a stimulus generator, for carrying out such an exercise, itself can be quite an involved task for a digital beamformer employing a large phased array antenna. This paper proposes an innovative design of a stimulus generator for the receive beamformer system. A reconfigurable hardware prototype, with a Xilinx Virtex-5 FPGA based architecture, is developed to generate IF stimulus for an 8-elements receive beamformer. It can provide a stimulus for upto four transmitting sources, each with programmable frequency, bandwidth, direction of arrival, S/N and interference. The beamformer performance testing for selective element failure can also be facilitated. Testing of a beamformer with larger phased array antenna can be achieved using multiple cards. The hardware test results are reported

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Index Terms

Computer Science
Information Sciences

Keywords

Digital beam former Generator Phased array antenna Test bed Xilinx Virtex-5 FPGA