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Circumventing Short Channel Effects in FETs: Review
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 117 - Number 17 |
| Year of Publication: 2015 |
| Authors: Khairnar Vinayak Prakash, Abhijeet Kumar, Prerana Jain |
10.5120/20648-3407
|
Khairnar Vinayak Prakash, Abhijeet Kumar, Prerana Jain . Circumventing Short Channel Effects in FETs: Review. International Journal of Computer Applications. 117, 17 ( May 2015), 24-30. DOI=10.5120/20648-3407
Abstract
The present paper aims at providing a thorough and yet a collective evaluation of some commendable research works done over the past decade with the aim for reducing short-channel effects (SCE). The necessity for development of these technologies arose as short channel effects such as – Drain-Induced Barrier Lowering (DIBL) and hot carrier effects arises manifold as the channel length is scaled further into the deep-submicron region to accommodate changes in ULSI applications. The review highlights some recent techniques to circumvent these effects in fabricated MOS devices, and in addition a short evaluation of strengths and weakness in each research works is also presented.
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