CFP last date
20 January 2025
Call for Paper
February Edition
IJCA solicits high quality original research papers for the upcoming February edition of the journal. The last date of research paper submission is 20 January 2025

Submit your paper
Know more
The week's pick
Responsive image
SFLA-Based Line Balancing and Task Optimization in Master-Slave Controlled Hanger Transportation Systems for Garment Production

Duc Hoang Nguyen
Random Articles
Reseach Article

FFT Architectures: A Review

by Shubhangi M. Joshi.
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 116 - Number 7
Year of Publication: 2015
Authors: Shubhangi M. Joshi.
10.5120/20350-2536

Shubhangi M. Joshi. . FFT Architectures: A Review. International Journal of Computer Applications. 116, 7 ( April 2015), 33-36. DOI=10.5120/20350-2536

@article{ 10.5120/20350-2536,
author = { Shubhangi M. Joshi. },
title = { FFT Architectures: A Review },
journal = { International Journal of Computer Applications },
issue_date = { April 2015 },
volume = { 116 },
number = { 7 },
month = { April },
year = { 2015 },
issn = { 0975-8887 },
pages = { 33-36 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume116/number7/20350-2536/ },
doi = { 10.5120/20350-2536 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:56:28.843381+05:30
%A Shubhangi M. Joshi.
%T FFT Architectures: A Review
%J International Journal of Computer Applications
%@ 0975-8887
%V 116
%N 7
%P 33-36
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Fast Fourier Transform (FFT) is one of the most efficient algorithm widely used in the field of modern digital signal processing to compute the Discrete Fourier Transform (DFT). FFT is used in everything from broadband to 3G and Digital TV to radio LAN's. Due to its intensive computational requirements, it occupies large area and consumes high power in hardware. Different efficient algorithms are developed to improve its architecture. This paper gives an overview of the work done of different FFT processor previously. The comparison of different architecture is also discussed.

References
  1. Miss. Jaishri Katekhaye, Mr. Amit Lamba, Mr. Vipin "REVIEW ON FFT PROCESSOR FOR OFDM SYSTEM" IJAICT Vol-1,NOV:2014
  2. Anwar Bhasha Pattan, Dr. Madhavi Latha "FastFourier Transform Architectures: A Survey" "IJAECT
  3. Weidong Li and Lars Wanhammar "LOW- POWER FFT PROCESSORS" "IJAECT
  4. Weidong Li and Lars Wanhammar"VLSI based FFT processor with improvement in computation speed and area reduction" "IJECSE 2013.
  5. H. Sorensen, D. Jones, M. Heideman, and C. Burrus, "Real-valued fast Fourier transform algorithms," IEEE Trans. Acoust. , Speech Signal Process. , vol. 35, no. 6, pp. 849–863, Jun. 1987.
  6. S. He and M. Torkelson, "Design and implementation of a 1024-point pipeline FFT processor," in Proc. IEEE Custom Integr. Circuits Conf. ,
  7. J. Lee, H. Lee, S. I. Cho, and S. S. Choi, "A high-speed two parallel radix-24 FFT/IFFT processor for MB-OFDM UWB systems," in Proc. IEEE Int. Symp. Circuits Syst. , May 2006, pp. 4719–4722.
  9. M. Ayinala, M. Brown, and K. K. Parhi, "Pipelined parallel FFT architectures via folding transformation," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 20, no. 6, pp. 1068–1081, Jun. 2012.
  10. R. Radhouane, P. Liu, and C. Modin, "Minimizing the memory requirement for continuous ?ow FFT implementation: Continuous ?ow mixed mode FFT (CFMM-FFT)," in Proc. IEEE Int. Symp. Circuits Syst. , May 2000, pp. 116–119.
  11. B. G. Jo and M. H. Sunwoo, "New continuous-?ow mixed-radix (CFMR) FFT processor using novel in-place strategy," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 5, pp. 911–919, May 2005.
  12. A. T. Jacobson, D. N. Truong, and B. M. Baas, "The design of a recon?gurable continuous-?ow mixed-radix FFT processor," inProc. IEEE Int. Symp. Circuits Syst. , May 2009, pp. 1133–1136.
  13. C. F. Hsiao, Y. Chen, and C. Y. Lee, "A generalized mixed-radix algorithm for memory-based FFT processors," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 1, pp. 26–30, Jan. 2010.
  14. P. -Y. Tsai and C. -Y. Lin, "A generalized con?ict-free memory addressing scheme for continuous-?ow parallel-processing FFT processors with rescheduling," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 19, no. 12, pp. 2290–2302, Dec. 2011.
  15. D. Reisis and N. Vlassopoulos, "Con?ict-free parallel memory accessing techniques for FFT architectures," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, pp. 3438–3447, Dec. 2008.
  16. H. Chi and Z. Lai, "A cost-effective memory-based real-valued FFT and Hermitian symmetric IFFT processor for DMT-based wire-line transmission systems," in Proc. IEEE Int. Symp. Circuits Syst. , May 2005, vol. 6,
  17. A. Wang and A. P. Chandrakasan, "Energy-aware architectures for a real-valued FFT implementation," in Proc. Int. Symp. Low Power Electron. Design, Aug. 2003, pp. 360–365.
  18. M. Garrido, K. K. Parhi, and J. Grajal, "A pipelined FFT architecture for real-valued signals," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 12, pp. 2634–2643, Dec. 2009.
  19. ManoharAyinala, Yingjie Lao, and Keshab K. Parhi, "An In-Place FFT Architecture for Real-Valued Signals," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 60, NO. 10, OCTOBER 2013.
Index Terms

Computer Science
Information Sciences

Keywords

Fast Fourier Transform (FFT) FFT architectures

Powered by PhDFocusTM