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FPGA Implementation of a Modified Turbo Encoder

by Rajagopal .a, Karibasappa .k, Vasundara Patel K.s
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 116 - Number 6
Year of Publication: 2015
Authors: Rajagopal .a, Karibasappa .k, Vasundara Patel K.s
10.5120/20341-2165

Rajagopal .a, Karibasappa .k, Vasundara Patel K.s . FPGA Implementation of a Modified Turbo Encoder. International Journal of Computer Applications. 116, 6 ( April 2015), 27-29. DOI=10.5120/20341-2165

@article{ 10.5120/20341-2165,
author = { Rajagopal .a, Karibasappa .k, Vasundara Patel K.s },
title = { FPGA Implementation of a Modified Turbo Encoder },
journal = { International Journal of Computer Applications },
issue_date = { April 2015 },
volume = { 116 },
number = { 6 },
month = { April },
year = { 2015 },
issn = { 0975-8887 },
pages = { 27-29 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume116/number6/20341-2165/ },
doi = { 10.5120/20341-2165 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:56:21.936917+05:30
%A Rajagopal .a
%A Karibasappa .k
%A Vasundara Patel K.s
%T FPGA Implementation of a Modified Turbo Encoder
%J International Journal of Computer Applications
%@ 0975-8887
%V 116
%N 6
%P 27-29
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Turbo convolutional codes (TCC) are excellent error correcting codes, however TCC decoding based on A-Posteriori Probability (APP) algorithm is computationally complex and the complexity is not significantly reduced even if puncturing mechanism is used. To overcome the above disadvantage turbo codes need to be concatenated with other coding techniques such that the decoding complexity is significantly reduced and at the same time the Signal to Noise Ratio (SNR) can be as close to the Shannon limit as possible. In this paper one such modification is described, whereby convolutional coding as well as block coding technique of Zig-Zag codes will be used. First the simulation results of the encoder using MATLAB are presented and then the FPGA results using Artix-7 board will be shown.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Recursive Systematic Coder (RSC) Zig-Zag codes Interleaver parallel concatenation Artix-7 FPGA.

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