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Different Techniques used for Carry Select Adder - A Review
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 116 - Number 3 |
| Year of Publication: 2015 |
| Authors: Rajwinder Kaur, Amit Grover |
10.5120/20313-2365
|
Rajwinder Kaur, Amit Grover . Different Techniques used for Carry Select Adder - A Review. International Journal of Computer Applications. 116, 3 ( April 2015), 1-4. DOI=10.5120/20313-2365
Abstract
To design the power and area proficient fast speed data path logic systems, the field of very large scale integration (VLSI) is the generally significant area of research where minimize the area and power is the more difficult task. In digital system, mostly adders lie in the crucial paths that affect the whole performance of the system. To perform the fast arithmetic functions in many data processing processors at low cost, carry select adder is the most suitable adder among the various adders. In this paper, we describe the different techniques which are used to design the proficient CSLA.
References
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