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Relative Performance Analysis of Different CMOS Full Adder Circuits

by Madhuresh Suman, Jagannath Samanta, Dibyendu Chowdhury, Jaydeb Bhaumik
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 114 - Number 6
Year of Publication: 2015
Authors: Madhuresh Suman, Jagannath Samanta, Dibyendu Chowdhury, Jaydeb Bhaumik
10.5120/19981-1922

Madhuresh Suman, Jagannath Samanta, Dibyendu Chowdhury, Jaydeb Bhaumik . Relative Performance Analysis of Different CMOS Full Adder Circuits. International Journal of Computer Applications. 114, 6 ( March 2015), 8-14. DOI=10.5120/19981-1922

@article{ 10.5120/19981-1922,
author = { Madhuresh Suman, Jagannath Samanta, Dibyendu Chowdhury, Jaydeb Bhaumik },
title = { Relative Performance Analysis of Different CMOS Full Adder Circuits },
journal = { International Journal of Computer Applications },
issue_date = { March 2015 },
volume = { 114 },
number = { 6 },
month = { March },
year = { 2015 },
issn = { 0975-8887 },
pages = { 8-14 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume114/number6/19981-1922/ },
doi = { 10.5120/19981-1922 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:51:58.785025+05:30
%A Madhuresh Suman
%A Jagannath Samanta
%A Dibyendu Chowdhury
%A Jaydeb Bhaumik
%T Relative Performance Analysis of Different CMOS Full Adder Circuits
%J International Journal of Computer Applications
%@ 0975-8887
%V 114
%N 6
%P 8-14
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Different adder circuits are elementary blocks in many contemporary integrated circuits, which are not only employed to perform addition operations, but also other arithmetic operations such as subtraction, multiplication and division. Full adder is the basic building block of any adder circuit. Area, speed and power are the three main design metrics for any VLSI circuit. In this work, eight different full adders' circuits based on standard (std. ) CMOS, CPL, 16-Transistor, DCVSL, PTL, TGA, 14-Transistor and 8-Transistor have been designed and implemented using Tanner EDA simulation tool. In this paper, authors have compared the propagation delay, power consumption and power delay product (PDP) of different full adder circuits by varying supply voltage (Vdd).

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Index Terms

Computer Science
Information Sciences

Keywords

CMOS full adder Propagation delay PDP DCVS PTL Tanner EDA tool.

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