CFP last date
20 January 2025
Reseach Article

Vedic Mathematics for Digital Signal Processing Operations: A Review

by Kaustubh M. Gaikwad, Mahesh S. Chavan
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 113 - Number 18
Year of Publication: 2015
Authors: Kaustubh M. Gaikwad, Mahesh S. Chavan
10.5120/19924-1503

Kaustubh M. Gaikwad, Mahesh S. Chavan . Vedic Mathematics for Digital Signal Processing Operations: A Review. International Journal of Computer Applications. 113, 18 ( March 2015), 10-14. DOI=10.5120/19924-1503

@article{ 10.5120/19924-1503,
author = { Kaustubh M. Gaikwad, Mahesh S. Chavan },
title = { Vedic Mathematics for Digital Signal Processing Operations: A Review },
journal = { International Journal of Computer Applications },
issue_date = { March 2015 },
volume = { 113 },
number = { 18 },
month = { March },
year = { 2015 },
issn = { 0975-8887 },
pages = { 10-14 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume113/number18/19924-1503/ },
doi = { 10.5120/19924-1503 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:51:26.664787+05:30
%A Kaustubh M. Gaikwad
%A Mahesh S. Chavan
%T Vedic Mathematics for Digital Signal Processing Operations: A Review
%J International Journal of Computer Applications
%@ 0975-8887
%V 113
%N 18
%P 10-14
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Speed improvement in Digital signal processing is considered to be challenging. High speed multipliers and adders are prime requirement for digital filters and for FFT operations. Vedic mathematics is an ancient scheme based on 16 formulas (sutras). These are simple and easy methods which can be directly applied for DSP computations. Many researchers have worked on multiplier designs using Vedic operators. Present paper deals with exhaustive review of literature based on Vedic mathematics. It shows that Vedic mathematics can be used for fast signal processing. Multipliers based on Vedic mathematics can be used for speed improvement, reduction in power consumption, complexity, area etc. Vedic mathematical algorithms can be proved efficient over traditional (existing) methods in FIR and IIR filters for providing effective results in de-noising of biomedical Signal.

References
  1. S. M. Khairnar, Sheetal Kapade, Naresh Ghorpade 2012 "Vedic mathematics- The cosmic software for implementation of fast algorithms", IJCSA-2012.
  2. Manorajan Pradhan, Rutuparna Panda, Sushant Kumar Sahu 2011, "Speed comparison of 16 X 16 vedic multipliers", International journal of computer applications, Vol. 21, No. 6, May 2011
  3. M. Pradhan , R. Panda, 2010 "Design and implementation of Vedic Multipliet", A. M. S. E. Journal, Series D, Computer Science and Statistics, Vol. 15, issue 2, 1-19 July 2010.
  4. Himanshu Thapliyal and M. B. srinavas, "A Novel Time-Area-Power Efficient Single Precision Floating Point Multiplier", Proceeding MAPLD 2005
  5. Aniruddha Kanhe, Shishir Kumar Das, Ankit Kumar Singh,2012 "Design and implementation of low power multiplier using vedic multiplication technique", International Journal of computer science and communication techniques, Vol. 3 No. 1 Jan-June 2012, 131-132
  6. Tarang Popat, Haushal Buch, "A novel architecture for fast polynomial division for binary coefficient", CDES, page 119-123. CSREA Press, (2008).
  7. Asmita Havelia,2012 "FPGA implementation of a vedic convolution algorithm", International Journal of Engineering research and applications, Vol. 2 , issue 1, Jan-Feb 2012, 678-884.
  8. Anuja George 2012 "A novel design of low power high speed SAMM and its FPGA implementation, International journal of computer applications, Volume 43, No. 4, April 2012
  9. L. Sriraman, T. N. Prabakar 2012, "Design and Implementation of Two Variable KCM using Multiplier using KCM and Vedic Mathematics ", in 1st International Conference on Recent Advancements in Information Technology, 2012.
  10. L. Sriraman, T. N. Prabakar 2012, "FPGA implementation of high performance multiplier using squarer", International Journal of Advanced Computer Engineering & Architecture Vol. 2, No. 2, June-December 2012
  11. Pouya Asadi and Keivan Navi 2007. "A New Low Power 32×32- bit Multiplier" World Applied Sciences Journal 2 (4): 341-347, 2007
  12. Himanshu Thapliyal and Hamid Rarbania 2004 "A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based On Ancient Indian Vedic Mathematics ", Proceedings of the International Conference on Embedded Systems and Applications, ESA '04 & Proceedings of the International Conference on VLSI, VLSI '04, June 21-24, 2004, Las Vegas, Nevada, USA.
  13. Sumit Vaidya, D. R,Dandekar, "Performance comparison of multipliers for power speed trade off in VLSI design", Proceeding ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing Pages 262-266.
  14. Sudhanshu Mishra, Manoranjan Pradhan 2012, "Synthesis comparison of Karatsuba multiplier using polynomial multiplication , vedic multiplier and classical multiplier", International journal of computer applications (0975- 8887) Vol. 41 No. 9, March 2012.
  15. Prashant Nair, Darshan Paranji, S. S. Rathod, "VLSI implementation of matrix diagonal method of binary multiplication", Proceedings of SPIT-IEEE Colloquium and International Conference, Mumbai, India, Vol. 2, 55
  16. Manoranjan Pradhan, Rutuparna Panda, Sushanta Kumar Sahu 2011, "MAC implementation using vedic multiplication algorithm", International journal of computer applications, Vol. 21 No. 7 May 2011.
  17. Nidhi Mittal, Abhijeet Kumar 2011, "Hardware implementation of FFT using vertically and crosswise algorithm?, International journal of computer applications, Vol. 35, No. 1 , December 2011.
  18. Ashish Raman, Anvesh Kumar, R. K. Sarin 2010, "High speed reconfigurable FFT design by Vedic mathematics", Journal of Computer Science and Engineering, Vol. 1 issue 1, May 2010
  19. Anvesh Kumar, Ashish Raman 2010, "Small Area Reconfigurable FFT Design by Vedic Mathematics", vol 5, 836-838.
  20. Ranjani Parthasarathi, Easwaran Raman, Karthik Sankaranarayanan, Lakshmi N. Chakrapan "A Reconfigurable Co-Processor for Variable Long Precision Arithmetic Using Indian Algorithms", The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001 at Rohnert Park, CA, USA,. 71-80.
  21. Laxman P. Thakre, Suresh Balpande,UmaehAkare, SudhairLande 2010, " Performance evaluation and Synthesis of Multiplier Used in FFT Operation Using conventional and Vedic Algorithm", International Conference on emerging trends in Engineering and Technology, 614-619.
  22. M. E. Paramasivam, Dr. R. S. Sabeenian 2010, "An Efficient Bit Reduction Binary Multiplication Algorithm using Vedic Methods" , 25-28.
  23. Anvesh Kumar, Ashish Raman 2010, "Low Power ALU Design by Ancient Mathematics", vol 5, 862-865, 2010
  24. Leonard Gibson Moses S, Thilagar M 2010, "VLSI Implementation of High Speed DSP algorithms using Vedic Mathematics" , International Journal of Computer Communication and Information System, Vol. 2. 119-122 Jul –Dec 2010.
  25. Parth Mehta, DhanashriGawelli 2009, " Conventional Versus Vedic Mathematical method for Hardware Implementation of a multiplier" , International Conference on emerging trends in Engineering and Technology, pp 640-642, 2009.
  26. Honey DurgaTiwari, GanzorigGankhuyag, Chan Mo Kim, Yong Beom Cho 2008, " Multiplier design based on ancient Indian Vedic Mathematics", International SoC Des ign Conference, pp 65-68.
  27. Ramachandran. S, Kirti. S. Pande, "Design, Implementation and Performance Analysis of an Integrated Vedic Multiplier Architecture" , International Journal Of Computational Engineering Research
  28. Purushottam D. Chidgupkar Mangesh T. Karad 2004, "The Implementation of Vedic Algorithms in Digital Signal Processing", Global Journal of Engineering Education, Vol. 8 No. 2.
  29. Ramesh Pushpagadan, Veenith Sukumaran, Rino, Dinesh , Sunder 2009, "High speed vedic multipliers for Digital Signal Processors", IETE journal of research, Vol. 55,issue 6, 2009, 282-286.
  30. Harpreet Singh Dhillon , Abhijit Mitra, "A Digital Multiplier Architecture using Urdhva Tiryakbhyam Sutra of Vedic Mathematics"www. academia. edu
  31. P V Rao, Cyril Raj Prasanna, S Ravi 2009, "Design and ASIC Implementation of Root Raised Cosine Filter", European Journal of Scientific Research, Vol. 31 No. 3 (2009), . 319-328
  32. Ashish Raman, Anvesh Kumar and R. K. Sarin, "High Speed Reconfigurable FFT Design by Vedic Mathematics", journal of computer science and engineering, volume 1, issue 1 may 2010, 59-64.
  33. Rana Mukharhi, Amit Kumar Chatterjee, Manishita Das 2011, "Implementation of an efficient multiplier architecture based on ancient indian vedic mathematics using System C", KIST journal of Science and Technology, Vol. 1 No. 1, 47-57, 2011.
  34. J. M. Rudagi, V. Ambli, V. Munavalli, R. Patil ,V. Sajjan 2011, "Design and implementation of efficient multiplier using Vedic mathematics", 3rd International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom 2011)
  35. Raman A. , Sarin R. K. , Khosala A. 2010, "Small area reconfigurable FFT design by using Vedic Mathematics", Computer and automation engineering (ICCAE), IEEE conference 26-28 Feb. 2010, 836 – 838.
  36. V. Vamshi Krishna, S. Naveen Kumar 2012, "High Speed, Power and Area efficient Algorithms for ALU using Vedic Mathematics" International Journal of Scientific and Research Publications, Volume 2, Issue 7, July 2012.
  37. Chi-Jui Chou, Satish Mohanakrishnan, Joseph B. Evans, " FPGA implementation of digital filters" , Proc. ICSPAT '93.
  38. J. B. Evans. 1993 "An efficient FIR filter architecture", In IEEE Int. Symp. Circuits and Syst. , pages 627–630,May 1993.
  39. Bharati Ainapure, Suvarna Joshi 2010," FPGA based FIR filter", International Journal of Engineering Science and Technology Vol. 2 (12), 7320-7323.
  40. Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner, 2006 "FPGA Implementation of High Speed FIR Filters Using Add and Shift Method", IEEE 2006
  41. Macpherson, K. N, "Rapid prototyping area efficient FIR filters for high speed FPGA implementation", Vision image and signal processing IEEE proceedings, volume- 153 , issue: 6 , 711 – 720.
  42. Vladimir M. Poucki, Andrej Zemva, Miroslav D. Lutovac, Tomaz Karcnik 2008, "Chebyshev IIR filter sharpening implemented on FPGA", 16 th Telecommunication forum TELFOR 2008, Serbia, Belgrade, Nov. 25-27.
  43. Bhattacharyya, A. Sharma P. , Murli N, Murti, "Development of FPGA based IIR Filter implementation of 2-degree of Freedom PID controller", IEEE Indian Conference 2011, 1-8.
  44. Ravinder Kaur, Ashish Raman, Member, IACSIT, Hardev Singh and Jagjit Malhotra 2011, "Design and Implementation of High Speed IIR and FIR Filter using Pipelining", International Journal of Computer Theory and Engineering, Vol. 3, No. 2, April 2011.
  45. S. M. Sajjadi, A. Joulaian, H. Ghomash 2004 "A new Implementation of DA-based IIR Filters on FPGA", 12th Iranian Conference on Electrical Engineering 2004.
  46. Manish Kansal, Hardeep Singh Saini, Dinesh Arora, 2011 "Designing & FPGA Implementation of IIR Filter Used for detecting clinical information from ECG" , International Journal of Engineering and Advanced Technology (IJEAT, Volume-1, Issue-1, October 2011
  47. R. Dutta, 2012"Power Efficient VLSI Architecture for IIR Filter using Modified Booth Algorithm", International Journal of advanced research in Technology, Vol. 2 Issue 1, 2012, 28-34.
  48. Zhenbin Gao , Xiangye Zeng , Jingyi Wang , Jianfei Liu,2008 "FPGA implementation of adaptive IIR filters with particle swarm optimization algorithm", 11th IEEE international conference on Communication Systems during 19-21 Nov. 2008 at Singapore,. 1364-1367.
  49. Lorca, F. G. Kessal, Dimigni 1997, "Efficient ASIC and FPGA implementations of IIR filters for real time edge detection", Image processing , IEEE conference proceedings 1997.
Index Terms

Computer Science
Information Sciences

Keywords

Vedic Mathematics Multiplier DSP Filter Design