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Design and Performance Analysis of Asynchronous GRO based Time to Digital Converter

by Anita Arvind Deshmukh, Akash Joshi, R. B. Deshmukh
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 112 - Number 14
Year of Publication: 2015
Authors: Anita Arvind Deshmukh, Akash Joshi, R. B. Deshmukh
10.5120/19736-1530

Anita Arvind Deshmukh, Akash Joshi, R. B. Deshmukh . Design and Performance Analysis of Asynchronous GRO based Time to Digital Converter. International Journal of Computer Applications. 112, 14 ( February 2015), 26-31. DOI=10.5120/19736-1530

@article{ 10.5120/19736-1530,
author = { Anita Arvind Deshmukh, Akash Joshi, R. B. Deshmukh },
title = { Design and Performance Analysis of Asynchronous GRO based Time to Digital Converter },
journal = { International Journal of Computer Applications },
issue_date = { February 2015 },
volume = { 112 },
number = { 14 },
month = { February },
year = { 2015 },
issn = { 0975-8887 },
pages = { 26-31 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume112/number14/19736-1530/ },
doi = { 10.5120/19736-1530 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:49:45.032383+05:30
%A Anita Arvind Deshmukh
%A Akash Joshi
%A R. B. Deshmukh
%T Design and Performance Analysis of Asynchronous GRO based Time to Digital Converter
%J International Journal of Computer Applications
%@ 0975-8887
%V 112
%N 14
%P 26-31
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

An Asynchronous Gated Ring Oscillator based Time to Digital Converter (A-GRO-TDC) is proposed. Gating functionality is added to a simple Ring Oscillator which drastically improves the system performance with asynchronous operation. Energy saving is possible due to scrambling and first order noise shaping. The proposed 9 bit A-GRO-TDC is implemented in Cadence using 0. 18µm digital CMOS Technology. Pre and post layout simulation with corner analysis shows good linearity. All these features with very little power between 16µW to 26µW make it suitable for IoT applications. It consumes an active area of 550µm x 410µm.

References
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  7. Ji Wang. Modeling And Implementation of All-Digital Phase-Locked Loop Based on Vernier Gated Ring Oscillator Time-to-Digital Converter. Master's Thesis. Department of Electrical and Information Technology, Faculty of Engineering, LTH, Lund University, October 2014.
  8. Jiang Chen; Huang Yumei and Hong Zhiliang, "A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology" Journal of Semiconductors, Vol. 34, No. 3. March 2013, pp. 035004-1 to 035004-5.
  9. Helal, B. M. ; Straayer, M. Z. ; Gu-Yeon Wei; Perrott, M. H. , "A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance," IEEE Journal of Solid-State Circuits, April 2008, vol. 43, no. 4, pp. 855,863,.
  10. Kyu-Dong Hwang; Lee-Sup Kim, "An area efficient asynchronous gated ring oscillator TDC with minimum GRO stages," Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30 -June 2 2010, pp. 3973-3976.
Index Terms

Computer Science
Information Sciences

Keywords

Gated Ring Oscillator (GRO) Time To Digital Converter (TDC) Quantization Noise Shaping Scrambling Delay Stages.

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