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Launch and Capture Power Reduction using Data Encoding and Precomputation Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 112 - Number 11 |
| Year of Publication: 2015 |
| Authors: R.deepika, V.sinduja |
10.5120/19713-1483
|
R.deepika, V.sinduja . Launch and Capture Power Reduction using Data Encoding and Precomputation Technique. International Journal of Computer Applications. 112, 11 ( February 2015), 28-31. DOI=10.5120/19713-1483
Abstract
Testing of VLSI circuits aims for high quality screening of circuits by targeting performance related faults. The main objective of testing is to generate compact test set which is used to detect multiple faults present in the circuit, which results in increase of switching activity hence the pattern should be optimized without losses in performance of the circuit. Design for Testability mechanism is used for launch-off shift and launch-off capture testing and it supports design partitioning approach in which one region is tested at a time results in launch and capture power reduction in a design flow compatible manner. Data encoding scheme is used to reduce the power dissipation by the means of reducing the switching activity which involves comparison of two bits at a time. By using precomputation technique which involves comparison of single bit at a time starting from its MSB to LSB, the power dissipation is reduced up to 20% compared to data encoding technique.
References
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