CFP last date
20 December 2024
Reseach Article

Test Method for Analog and Mixed Signal Device based OBIST and IDDQ

by Mradul Kumar Ojha, Shyam Akashe
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 112 - Number 1
Year of Publication: 2015
Authors: Mradul Kumar Ojha, Shyam Akashe
10.5120/19633-1207

Mradul Kumar Ojha, Shyam Akashe . Test Method for Analog and Mixed Signal Device based OBIST and IDDQ. International Journal of Computer Applications. 112, 1 ( February 2015), 38-44. DOI=10.5120/19633-1207

@article{ 10.5120/19633-1207,
author = { Mradul Kumar Ojha, Shyam Akashe },
title = { Test Method for Analog and Mixed Signal Device based OBIST and IDDQ },
journal = { International Journal of Computer Applications },
issue_date = { February 2015 },
volume = { 112 },
number = { 1 },
month = { February },
year = { 2015 },
issn = { 0975-8887 },
pages = { 38-44 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume112/number1/19633-1207/ },
doi = { 10.5120/19633-1207 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:48:19.795748+05:30
%A Mradul Kumar Ojha
%A Shyam Akashe
%T Test Method for Analog and Mixed Signal Device based OBIST and IDDQ
%J International Journal of Computer Applications
%@ 0975-8887
%V 112
%N 1
%P 38-44
%D 2015
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper describes a testing method to analyze analog and mixed signal device based on oscillation test process, which in turn is dependent on the BIST (Built In Self-Test method) appropriate for function based and structure based testing of analog and mixed signal device. During this test process, the test circuit is converted into oscillator with the help of addition of an extra circuitry in their feedback path. The faults present inside the test circuit that because an affordable deviation of the oscillation frequency and their amplitude from its value are detected. Through, this test method, there is no required of any test vector to apply. Therefore, the test vector generation drawbacks are eliminated and also the test time is reduced because a limited number of oscillation frequencies are calculated for each test circuit. Oscillation-test strategy and I_DDQ test method are very suitable for further wafer-probe testing for final production of testing. The application of this test method takes benefits for good fault coverage by using of a simple OBIST technique, necessity to apply that does not required any test signal generation and combines it with I_DDQ (quiescent supply current) testing to provide a fault confirmation. During this paper, the simulation results of this test method have been provided through some examples like continuous time state variable filter.

References
  1. Jacob A. Abraham and Jeongjin Roh, "A Comprehensive Signature Analysis Scheme for Oscillation Test," IEEE Transactions on Computer Aided Design, vol. 22, no. 10, pp. 1409-1423, Oct. 2003.
  2. M. H. Assaf, Sunil R. Das, W. Hermas and W. B. Jone, "Promising Complex ASIC Design Verification Methodology," Proceeding IEEE Conference on Instrumentation and Measurement Technology (IMTC), pp. 1-6, May 2007.
  3. S. R. Das, "Self-testing of Embedded cores-based Systems with Built-in Hardware," Proceeding, Institute of Electrical Engineering- Circuit Devices Systems, vol. 152, no. 5, pp. 539-546, Oct. 2005.
  4. Andrew Richardson, "Design-for-test Strategies Analogue and Mixed Signal Integrated Circuits," Proceeding of 38th Midwest Symposium on Circuits and systems, vol. 2, no. 4, pp. 1139-1144, Aug. 1995.
  5. S. M. Saeed, "Design for Testability support for Lunch and Capture Power Reduction in Lunch-off-Capture," IEEE Transactions of Very Large Scale Integration (VLSI) Systems, vol. 22, no. 8, pp. 516-521, March 2014.
  6. I. Pomeranz and S. M. Reddy, "Transparent DFT: a Design for Testability and Test generation approach for Synchronous Sequential Circuits," IEEE Transaction of Computer-Aided Design of Integrated Circuit and Systems, vol. 25, no. 6, pp. 1170-1175, June 2006.
  7. M. H. Assaf and Maryam Fathi, "Built in Hardware for Analog Circuitry Testing," Electronics, Robotics and Automotives Mechanics Conference, no. 2, pp. 14-19, Sep-Oct 2008.
  8. S. Umezu and M. Hashizume, "A Built-in Supply Current Test Circuits for Pin opens in Assembled PCBs," International Conference on Electronics Packaging (ICEP), pp. 227-230, April 2014.
  9. Sunil R. Das, "Self-testing of Embedded cores-based Systems with Built-in-Hardware," Proceeding IEEE Transaction on Circuit, Devices and Systems, vol. 152, no. 5, pp. 539-546, Oct. 2005.
  10. Daniel Arbet, Viera Stopjakova, Libor Majer and Gabriel Nagi, " New OBIST using On-chip compensation of process variations toward increasing Fault Delectability in Analog ICs," IEEE Transactions on Nanotechnology, vol. 12, no. 4, pp. 486-497, July 2013.
  11. Sergio Callegari and G. Setti, "Complex Oscillation based Test and its Application to Analog Filter," IEEE transaction on circuits and systems, vol. 57, no. 5, pp. 956-969, May 2010.
  12. Miljana Milic and Vanco Litovski, "Oscillation based Analog Testing- a case study," MIPRO, Proceedings of the 34th International Convention, no. 5, pp. 96-101, May 2011.
  13. Daniel Arbet and Gabriel Nagi, "Efficiency of Oscillation-based BIST in 90nm CMOS Active Analog Filter," 16th International Symposium on IEEE, Design and Diagnostics of Electronic Circuits & Systems (DDECS), no. 4, pp. 263-266, April 2013.
  14. Daniel Arbet, Juraj Brenkus and Viera Stopjakova, "Oscillation-based Built-in Self Test of Integrated Active Analog Filters," International Conference, Applied Electronics (AE), no. 2, pp. 1-4, Sept. 2011.
  15. Jila Zakizadeh and Sunil R. Das, "Testing Analog and Mixed Signal Circuits with Built-in Hardware, A New approach," Proceeding of IEEE Conference on Instrumentation and Measurement Technology IMTC 2005, no. 3, pp. 166-171, May 2005.
  16. Radoslaw M. Biernacki and Johan W. Bandler, "Multiple-fault Location of Analog Circuits," IEEE Transaction on Circuits and Systems, vol. 28, no. 5, pp. 361-367, May 2003.
  17. Linda Milor and S. Alberto Vincentelli, "Computing Parametric Yield accurately and efficiently," Proceeding of IEEE Conference on Computer-Aided Design, pp. 116-119, Nov. 2008.
  18. Ender Yilmez and Shofner Geoff, "Fault Analysis and Simulation of Large Scale Industrial Mixed signal," Automation, Design and Test in Europe Conference & Exhibition, pp. 565-570, March 2013.
Index Terms

Computer Science
Information Sciences

Keywords

Built In Self Test (BIST) Oscillation based Built In Self Test (OBIST) Quiescent supply current (I_DDQ) System On Chip (SOC) Design for testability (DFT) Integrated Circuit (IC) Circuit under test (CUT) analog and mixed signal (AMS).