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Reduction of Leakage Power in Half- Subtractor using AVL Technique based on 45nm CMOS Technology
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 111 - Number 1 |
| Year of Publication: 2015 |
| Authors: Anand Singh Narwariya, Shyam Akashe |
10.5120/19504-1102
|
Anand Singh Narwariya, Shyam Akashe . Reduction of Leakage Power in Half- Subtractor using AVL Technique based on 45nm CMOS Technology. International Journal of Computer Applications. 111, 1 ( February 2015), 31-35. DOI=10.5120/19504-1102
Abstract
The analytical paper of arithmetic circuits plays an important role in designing of any VLSI system. Subtractor is one of them. Half Subtractor is being designed using Adaptive Voltage Level (AVL) techniques. This design consumed less power as compare to conventional design. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. This paper represents how to control power using AVL techniques. The AVL technique based Half Subtractor compared to conventional design that based on power consumption, propagation delay, speed and layout area is more preferred. Power consumption of the projected cell is measured and compared. The result shows that there is a significant reduction in power consumption for this proposed cell with the AVL technique. This styal is much useful in designing the system that consumed less power. The circuit is simulated on Cadence tools in 45 nanometer CMOS technology.
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