The week's pick
Random Articles
Reseach Article
Minimizing Power Consumption in CMOS Full Subtractor using SVL Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 110 - Number 9 |
| Year of Publication: 2015 |
| Authors: Anand Singh Narwariya, Shyam Akashe |
10.5120/19348-1071
|
Anand Singh Narwariya, Shyam Akashe . Minimizing Power Consumption in CMOS Full Subtractor using SVL Technique. International Journal of Computer Applications. 110, 9 ( January 2015), 45-49. DOI=10.5120/19348-1071
Abstract
Full Subtractor using Self Controllable Voltage Level (SVL) Technique is designed in this paper. The circuit can supply an increased dc voltage to an active-load circuit required or can decrease the dc voltage supplied to a load circuit under standby mode is developed. Full Subtractor is a consumed low power and low Leakage as compare to conventional design with SVL technique. We may reduce the value of total power dissipation by applying the U-SVL (upper Self Controllable voltage level) technology in which the supply potential is increased and L-SVL (Lower Self Controllable voltage level) technology in which the ground potential is raised. The analysis paper represents how to control power using SVL techniques. The SVL technique based Full Subtractor compared to conventional design that based on power consumption, propagation delay speed and layout area is more preferred. Low-power techniques projected to reduce power in nanoscale CMOS-Very Large Scale Integration (VLSI) systems, Using SVL technique. The result shows that there is significant reduction in Power assimilation of Full Subtractor in reference mode. This design is much useful in designing the system that low power consumed. The circuit is designed using Cadence Tools in 45nm Technology.
References
- B. Dilli Kumar and M. Bharathi, "Design and Analysis of Adaiabatic Full Subtractor for Low Power Applications", International Journal of Advanced Scientific and Technical Research, vol. 1, No. 3, pp. 219-231.
- D. A. Antoniadis, I. Aberg, C. N. Chleirigh, O. M. Nayfeh, A. Khakifirooz and J. L. Hoyt, "Continuous MOSFET performance increase with device scaling: The role of strain and channel material innovations", IBM Journal Research Development, vol. 50, no. 4, pp. 363–376, Jul. 2006.
- K. Roy, S. Mukhopadhyay and H. Mahamoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deep sub-micrometer CMOS circuits", in Proceeding IEEE, vol. 91, no. 2, pp. 305– 327,Feb. 2003.
- S. Dutta, S. Nag and K. Roy, "ASAP: A Transistor Sizing tool for speed, area, and power optimization of static CMOS circuits", IEEE International Symposium on Circuits and Systems, vol. 1 pp. 61-64, June. 1994.
- B. Dilli Kumar and M. Bharathi, "Design and Analysis of Adiabatic Full Subtractor for Low Power Applications", International Journal of Advanced Scientific and Technical Research, vol. 1, no. 3, pp. 219-231.
- P. Sharma, Anjali Sharma and Richa Singh, "Design and analysis of area and power efficient 1-bit Full Subtractor using 120nm technology," International Journal of computer application, vol. 88, no. 12, pp. 1-42, Feb. 2014.
- Tanvi Sood and Rajesh Mehra, "Design a Low Power Half-Subtractor Using . 90?m CMOS Technology," IOSR Journal of VLSI and Signal Processing , vol. 2, no. 3, pp. 57-61, Jun 2013.
- Mutoh S, "1-V Power supply high-speed digital circuit technology with multi-threshold voltage CMOS", IEEE J. Solid State Circuits, vol. 30, pp. 847-854, August 1995.
- Hemantha S, Dhawan A and Kar H, "Multi-threshold CMOS design for low power digital circuits", TENCON 2008-2008 IEEE Region 10 Conference, pp. 1-5, 2008.
- H. Thapliyal, M. B Srinivas, H. R Arabnia, "Reversible Logic Synthesis of Half, Full and Parallel Subtractors", Proceeding of the 2005 International Conference on Embedded Systems and Applications, Las Vegas, pp. 165-181.
- Phanikumar M and N. Shanmukha Rao, "A Low Power and High Speed Design for VLSI Logic Circuits Using Mult-Threshold Voltage CMOS Technology", International Journal of Computer Science and Information Technologies (IJCSIT), vol. 3(3), pp. 4131-4133, 2012.
- H. Thapliyal and N. Ranganathan, "Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuit", Proceeding of the 22nd International Conference on VLSI Design, New Delhi, India, pp. 511-516, 2009.
- Majid Mohammadi, Mohammad Eshghi, Majid Haghparast and Abbas Bahrololoom, "Design and Optimization of Reversible BCDAdder/Subtractor Circuit for Quantum and Nanotechnology Based Systems", World Applied Sciences Journal, vol. 4, no. 6, pp. 787-792, 2008.
- Zimmermann R. and Fichtner W. , "Low-power logic styles: CMOS versus pass-transistor logic", IEEE Journal Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, 1997.
- J. Kao, A. Chandrakasan, and D. Antoniadis, "Transistor sizing issues and tool for multi-threshold CMOS technology", in proceeding 34th DAC, pp. 409-414, 1997.
- Monpapassorn, "Programmable wide range voltage adder/Subtractor and its applications an encoder", IEEE Proceeding of Circuits Devices and Systems, vol. 152, pp. 697-702, 2005.
- R. Fried and C. C. Enz, "Simple and accurate voltage adder/Subtractor", Electronics Letters, vol. 33, pp. 944-945.
- Andrew Bailey, Ahmad AlZahrani, Guoyuan Fu, Jia Di and Scott Smith, "Multi-threshold Synchronous Circuit Design for Ultra-Low Power", Journal of Low power Electronics, vol. 4, pp. 1-12, 2008.
Index Terms
Keywords