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Article:Reconfigurable FFT System on Chip (SOC)
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 11 - Number 5 |
| Year of Publication: 2010 |
| Authors: G. Venkataramana Sagar, Dr. K. Srinivasa Rao |
10.5120/1575-2107
|
G. Venkataramana Sagar, Dr. K. Srinivasa Rao . Article:Reconfigurable FFT System on Chip (SOC). International Journal of Computer Applications. 11, 5 ( December 2010), 35-38. DOI=10.5120/1575-2107
Abstract
With onset of paradigms of System On Chip (SOC) to design a module for real time applications or voice codec’s, The SOC’s have different requirements for operands precision we propose a reusable FFT [2] using reconfigurable multiplier [6]. How ever, the FFT perform either combining N and N/2 bit multiplications in the same N bit tree multiplier. The key challenges in designing a reusable FFT are to limit the impact of flexibility on power operations that are needed for FFT butterfly to perform better than a conventional, dedicated FFT butterfly.
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