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ASIC Design of Reversible Adder and Multiplier
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 109 - Number 10 |
| Year of Publication: 2015 |
| Authors: B.sai Abhinav, M.jaipal Reddy, Y.siva Kumar, and S.sivanantham |
10.5120/19222-0638
|
B.sai Abhinav, M.jaipal Reddy, Y.siva Kumar, and S.sivanantham . ASIC Design of Reversible Adder and Multiplier. International Journal of Computer Applications. 109, 10 ( January 2015), 6-10. DOI=10.5120/19222-0638
Abstract
Reversible logic is one of the promising research areas in low power applications such as quantum computing, optical information processing and low power CMOS design. In this paper we present a reversible carry look ahead adder and an array multiplier. The circuits are designed such that they result in less garbage outputs, constant inputs, and less gate count compared to previous existing designs. We also gain better improvements in terms of power and area when compared to conventional adders and multipliers. The implemented designs are simulated using NC launch and synthesized by RTL compiler.
References
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