CFP last date
20 January 2025
Call for Paper
February Edition
IJCA solicits high quality original research papers for the upcoming February edition of the journal. The last date of research paper submission is 20 January 2025

Submit your paper
Know more
The week's pick
Responsive image
SFLA-Based Line Balancing and Task Optimization in Master-Slave Controlled Hanger Transportation Systems for Garment Production

Duc Hoang Nguyen
Random Articles
Reseach Article

Cost Efficient Fault Tolerant Decoder in Reversible Logic Synthesis

by Md. Riazur Rahman
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 108 - Number 2
Year of Publication: 2014
Authors: Md. Riazur Rahman
10.5120/18881-0160

Md. Riazur Rahman . Cost Efficient Fault Tolerant Decoder in Reversible Logic Synthesis. International Journal of Computer Applications. 108, 2 ( December 2014), 7-12. DOI=10.5120/18881-0160

@article{ 10.5120/18881-0160,
author = { Md. Riazur Rahman },
title = { Cost Efficient Fault Tolerant Decoder in Reversible Logic Synthesis },
journal = { International Journal of Computer Applications },
issue_date = { December 2014 },
volume = { 108 },
number = { 2 },
month = { December },
year = { 2014 },
issn = { 0975-8887 },
pages = { 7-12 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume108/number2/18881-0160/ },
doi = { 10.5120/18881-0160 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:41:55.830853+05:30
%A Md. Riazur Rahman
%T Cost Efficient Fault Tolerant Decoder in Reversible Logic Synthesis
%J International Journal of Computer Applications
%@ 0975-8887
%V 108
%N 2
%P 7-12
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Fault Tolerant reversible decoders are the prerequisite of high performance computing systems. In this paper, an optimized reversible fault tolerant decoder has been proposed by using novel cost effective gates named Reversible Fault Tolerant Decoder (RDC) and Double Fredkin Gate (DFG). Several lower bounds on the numbers of gates, garbage and quantum costs are also proposed to generalize the architecture of n-to-2n reversible decoder. The comparative performance analysis shows that the proposed design outperforms the existing designs in terms of number of gates used, quantum cost, delay, ancilla inputs and design complexity.

References
  1. Rolf Landauer. 1961. Irreversibility and heat generation in the computing process. IBM journal of research and development. Vol. 44, 261-269.
  2. Charles H. Bennett. 1973. Logical reversibility of computation. IBM Journal of Research and Development. Vol. 17. No. 6, pp. 525–532.
  3. Andrew M. Steane. 1998. Quantum computing. Reports on Progress in Physics. No. 61. No. 2. Feb(1998). 117-173. DOI: http://dx. doi. org/10. 1088/0034-4885/61/2/002
  4. Konrad Walus and T. J. Dysart, G. A. Jullien and R. A. Budiman. 2004. QCA Designer: A rapid design and simulation tool for quantum-dot cellular automata. IEEE Transactions on Nanotechnology. Vol. 3. No. 1. 26-31.
  5. Gheorghe Paun, Rozenberg Grzegorz, and Arto Salomaa. 1998. DNA computing: new computing paradigms. Springer-Verlag New York. Inc. Secaucus. NJ. ISBN:3540641963.
  6. Ketan N. Patel, John P. Hayes and Igor L. Markov. 2004. Fault testing for reversible circuits. . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 23. No. 8. 1220-1230.
  7. Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, and Hafiz Md. Hasan Babu. 2012. An Efficient Approach for Designing and Minimizing Reversible Programmable Logic Arrays. In Proceedings of the 22nd Great Lakes Symposium on VLSI. 215-220. ACM. New York. NY. USA.
  8. R. K. James, T. K. Shahana, K. P. Jacob, and S. Sasi. 2007. Fault tolerant error coding and detection using reversible gates, IEEE TENCON.
  9. Rubaia Rahman, Lafifa Jamal, Hafiz Md. Hasan Babu. 2011. Design of Reversible Fault Tolerant Programmable Logic Arrays with Vector Orientation. International Journal of Information and Communication Technology Research, Vol 1 No. 8, December.
  10. Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury and Hafiz Md. Hasan Babu. 2008. Efficient approaches for designing reversible Binary Coded Decimal adders. Microelectronics journal. Vol. 39. No. 12. 1693-1703.
  11. Richard P. Feynman. 1985. Quantum mechanical computers. Optics News. Vol. 11. No. 2. 11-20 .
  12. Tommaso Toffoli. 1980. Reversible computing. MIT Lab for Computer Science. Seventh Colloquium Noordwijkerhout. The Netherlands. Vol. 85. 632–644.
  13. Edward Fredkin and Tommaso Toffoli. 1982. Conservative logic. International Journal Of Theoretical Physics. Kluwer Academic Publishers-Plenum Publishers. Vol. 21. No. 3, 4. 219–253.
  14. Behraoz Parhami. 2006. Fault tolerant reversible circuits. In Proceedings of the 40th Asimolar Conference Signals, Systems and Computers. Pacific Grove. CA. 1726–1729.
  15. Asher Peres. 1985. Reversible Logic and Quantum Computers. Physics Review A. Vol. 32. No. 6. 3266–3276.
  16. Majid Haghparast and Keivan Navi. 2008. A Novel Reversible BCD Adder for Nanotechnology Based Systems. American Journal of Applied Sciences. Vol. 5. No. 3. 282-288. ISSN: 1546-9239
  17. Sajib Kumar Mitra and Ahsan Raja Chowdhury. 2012. Minimum cost fault tolerant adder circuits in reversible logic synthesis. In Procedings of the 25th International Conference on VLSI Design (VLSID). Hyderabad. IEEE. 334-339.
  18. Sajib Kumar Mitra, Tamzida Sultana, Shahed Anwar and Ahsan Raja Chowdhury. 2011. Efficient Approach to design Reversible Fault Tolerant Cyclic Redundancy Check Circuit. In Proceedings of the 2nd International Conference on Signals, Systems & Automation (ICSSA-11). G H Patel College of Engineering & Technology. Gujarat. India.
  19. Himanshu Thapliyal and Nagarajan Ranganathan. 2011. A New Reversible Design of BCD Adder. In Proceedings of the Design Automation and Test in Europe (DATE). Grenoble. France. 1180-1183.
  20. Marek Perkowski, Martin Lukac, Mikhail Pivtoraiko and et al. 2003. A hierarchical approach to computer-aided design of quantum circuits. In 6th International Symposium on Representations and Methodology of Future Computing Technology. 201-209.
  21. Md. Shamsujjoha and Hafiz Md. Hasan Babu. 2013. A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor. 26th International Conference on VLSI Design. 368-373. India.
  22. S. N. Mahammad and K. Veezhinathan. 2010. Constructing online testable circuits using reversible logic, IEEE Transactions on Instrumentation and Measurement, vol. 59, 101–109.
Index Terms

Computer Science
Information Sciences

Keywords

Reversible Decoder Circuit Quantum Computing Fault Tolerant Low Power Computing.

Powered by PhDFocusTM