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Design of Low Voltage Low Power OP-AMP using DTMOS Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 106 - Number 18 |
| Year of Publication: 2014 |
| Authors: Bhanu Kumar G, Vasudeva Reddy T |
10.5120/18708-9850
|
Bhanu Kumar G, Vasudeva Reddy T . Design of Low Voltage Low Power OP-AMP using DTMOS Technique. International Journal of Computer Applications. 106, 18 ( November 2014), 36-38. DOI=10.5120/18708-9850
Abstract
This paper demonstrates the design of low voltage, low power CMOS op-amp using DTMOS technique for low-power applications. The design goal is to achieve high gain, phase margin and minimum power dissipation at lower supply voltage. DTMOS transistor is proposed in this paper for the design of op-amp which replaces the normal CMOS transistors for designing a low power, low voltage two stage op-amp. A dc gain of 96. 38 dB, a phase margin of 71. 46º by achieving a unity gain bandwidth of 4. 077 MHz while operating at 1V supply voltage. The performed simulation results show a power dissipation of 12. 19 µW is achieved under 5 pF load in this design. The design and analysis is performed using 180 nm CMOS technology in Cadence Virtuoso ADE.
References
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- Saber Izadpanah Tous1, Mahmoud Behroozi, Hooman Nabovati and Vahid RR Asadpour, "Overview of low-voltage low-power design techniques and design of a low-voltage low-Power low-noise operational amplifier" Department of Electrical Engineering, Sadjad Institute of higher Education, Mashhad, Iran, 2013.
- Saber Izadpanah Tous, Mahmoud Behroozi, Vahid sadpoor, "Design of 0. 4 V operational amplifier using low-power techniques" Iran, Vol 2, 2013.
- S. Izadpanah Tous, M. Behroozi, S. A. Ziafati Bagherzadeh, B. Razeghi, V. Asadpour, "Design of a High Performance CMOS Operational Amplifier Using DTMOS Technique", 11th Sharif Conference on Future Electronics (SCFE 2013), Iran, March 2013.
- H. F. Achigui, C. J. B. Fayomi, and M. Sawan, "1 V DTMOS based class AB operational amplifier: Implementation and experimental results," IEEE Journal of Solid-State Circuits, Vol. 41, No. 11, 2006.
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