CFP last date
20 January 2025
Call for Paper
February Edition
IJCA solicits high quality original research papers for the upcoming February edition of the journal. The last date of research paper submission is 20 January 2025

Submit your paper
Know more
The week's pick
Responsive image
SFLA-Based Line Balancing and Task Optimization in Master-Slave Controlled Hanger Transportation Systems for Garment Production

Duc Hoang Nguyen
Random Articles
Reseach Article

Energy Efficiency Enhancement for 45nm 1Mb SRAM Array Structures

by Mamatha Samson, Madhulatha
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 105 - Number 5
Year of Publication: 2014
Authors: Mamatha Samson, Madhulatha
10.5120/18373-9531

Mamatha Samson, Madhulatha . Energy Efficiency Enhancement for 45nm 1Mb SRAM Array Structures. International Journal of Computer Applications. 105, 5 ( November 2014), 16-20. DOI=10.5120/18373-9531

@article{ 10.5120/18373-9531,
author = { Mamatha Samson, Madhulatha },
title = { Energy Efficiency Enhancement for 45nm 1Mb SRAM Array Structures },
journal = { International Journal of Computer Applications },
issue_date = { November 2014 },
volume = { 105 },
number = { 5 },
month = { November },
year = { 2014 },
issn = { 0975-8887 },
pages = { 16-20 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume105/number5/18373-9531/ },
doi = { 10.5120/18373-9531 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:36:55.405700+05:30
%A Mamatha Samson
%A Madhulatha
%T Energy Efficiency Enhancement for 45nm 1Mb SRAM Array Structures
%J International Journal of Computer Applications
%@ 0975-8887
%V 105
%N 5
%P 16-20
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Energy efficiency is a supreme design concern in many ultralow-power applications. In such applications, high density Static Random-Access Memory (SRAM) plays a significant role. This paper explores and analyzes 1Mb SRAM array structures for energy efficiency improvement by adopting circuit modifications and inclusion of charge sharing circuits. The analysis shows that the array structure optimization and charge accumulator circuits can improve the energy efficiency for the same SRAM bit density and the same supply voltage.

References
  1. D. Somasekhar, Yibin Ye, Kaushik Roy, "An Energy Recovery Static RAM Memory Core, In Proc. 1995 Symposium on Low Power Electronics", San Jose, CA, October 9-1, 1995
  2. N. Tzartzanis and W. C. Athas, "Energy recovery for the design of high-speed, low power static RAMs," In Proc. IEEE International Symposium on Low Power Electronics and Design pp. 55–60, 1996
  3. Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou "Energy Recovering Static Memory" In Proc. ISLPED'02, Monterey, California, USA, August 12–14, 2002
  4. Joohee Kim,M. C Papaefthymiou, In Proc. "Constant –Load Energy Recovery Memory For Low Power, International Symposium on Low power Electronics and Design,pp. 240-243. 2004
  5. Joohee Kim, C. H. Ziesler, "Fixed-Load Energy Recovery Memory for Low Power", In Proc. International Symposium on Very Large Scale Integration. Systems, pp. 145. 6,2004
  6. Shunji Nakata in "Recent Patents on Electrical Engineering, 2009, Vol. 2,No. 1
  7. Byung-Do Yang "A Low Power SRAM Using Bit Line Charge –Recycling for Read and WriteOperations in IEEE Journal of Solid-State Circuits, Vol. 45, No. 10, October 2010
  8. Jun-Jun Yu, Peng-Jun Wang "Design of Adiabatic SRAM Based on CTGAL Circuit". In Proc. The 8thInternational Conference on Solid State and Integrated-Circuit Technology, October 23-26, 2006
  9. Hao-I Yang,Ssu-Yun Lai,and Wei Hwang "Low-Power Floating Bit line 8-T SRAM Design with Write Assistant Circuits" In Proc. IEEE International SOC Conference ,October, 2008
  10. Shunji Nakata,Hirotsugu Suzuki,Ryota Honda,Takahito Kusumoto,Shinjchiro Mutoh, Hiroshi Makino, Masayuki Makino, Masayuki Miyama and Yoshio Matsuda " Adiabatic SRAM with a shared Access Port using a Controlled Ground Line and Step-Voltage Circuit" In Proc. IEEE International Symposium on Circuits and Systems, ISCAS 2010, pp. 2474-2477, 2010.
  11. Keejong Kim, Hamid Mahmoodi and Kaushik Roy "A Low Power SRAM Using Bit- Line Charge-Recycling" IEEE Journal of Solid State Circuits, vol. 43, no. 2, pp. 446-458, 2008
  12. Byung-Do Yang "A Low Power SRAM Using Bit Line Charge –Recycling for Read and Write Operations in IEEE Journal of Solid-State Circuits, Vol. 45, No. 10, October 2010
  13. S. Moriwaki1, Y. Yamamoto1, A. Kawasumi1, T. Suzuki2, S. Miyano1, T. Sakurai3 and H. Shinohara1,"A 13. 8pJ/Access/Mbit SRAM with Charge Collector circuits for Effective Use of Non Selected Bit Line Charges". In Proc. Symposium on VLSI Circuits Digest of Technical Papers, 2012
  14. Seevinck, F. J. List and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells, " Solid-State Circuits, IEEE Journal of, vol. 22, 1987 pp. 748-754
Index Terms

Computer Science
Information Sciences

Keywords

Six-transistor (6T) Static Random-Access Memory (SRAM) energy efficiency minimum energy SRAM charge-share

Powered by PhDFocusTM