The week's pick
Random Articles
Reseach Article
A Review of Noise Susceptible Transistor in Dynamic Logic Circuits
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 105 - Number 17 |
| Year of Publication: 2014 |
| Authors: Neha Saini, Brij Bihari Soni, Brahmi Shrman |
10.5120/18468-9857
|
Neha Saini, Brij Bihari Soni, Brahmi Shrman . A Review of Noise Susceptible Transistor in Dynamic Logic Circuits. International Journal of Computer Applications. 105, 17 ( November 2014), 10-16. DOI=10.5120/18468-9857
Abstract
Noise is becoming a major concern in digital systems due to the insistent scaling development in devices and interconnections. In this paper disputes related to process variations, timing, noise suppression, and power are investigated here for performance optimization. A weak PMOS keeper logic is used to improve the scaling of dynamic gates. The keeper has an overhead of one field-effect transistor per gate plus a portion of a shared current mirror. This keeper circuit technique is proposed in this paper for simultaneous power reduction and speed enhancement of domino integrated circuits. The threshold voltage of the keeper logic is modified during circuit operation to decrease the contention current without giving up noise immunity. The charge sharing can also be eliminated by pre-charging internal node.
References
- Hailong Jiao, Student Member, IEEE, and VolkanKursun, "Reactivation Noise Suppression with Sleep Signal Slew Rate Modulation in MTCMOS Circuits" IEEE TransactionsOn Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 3, March 2013.
- ManishaPattanaik,Muddala V. D. L. Varaprasad and Fazal Rahim Khan, " Ground Bounce Noise Reduction of Low leakage 1-bit Nano-CMOS based Full Adder Cells for Mobile Applications", International conference on electronics devices ICEDSA year 2010.
- Gaetano Palumbo,MelitaPennisi,and Massimo Alioto, "A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates", IEEE Transactions On Circuits And Systems—I: Regular Papers, Vol. 59, No. 10, October 2012.
- Kumar Yelamarthi and Chien-In Henry Chen, "Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations", IEEE Transactions on Semiconductor Manufacturing, Vol. 25, No. 2, May 2012.
- F. Mendoza-Hern´andez, M. Linares, V. H. Champac and A. D´?az-S´anchez,"A New Technique For Noise-Tolerant Pipelined Dynamic Digital Circuits", 2002 IEEE.
- Li Ding and PinakiMazumder "On Circuit Techniques to Improve Noise Immunity of CMOS Dynamic Logic" IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 9, September.
- P. Heydari and M. Pedram, "Ground bounce in digital VLSI circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 11, no. 2, pp. 180–185, Apr. 2003.
- Z. Liu and V. Kursun, "Charge recycling between virtual power and ground lines for low energy MTCMOS," in Proc. IEEE/ACM Int. Symp. Qual. Electron. Design, Mar. 2007.
- H. Jiao and V. Kursun, "Tri-mode operation for noise reduction and data preservation in low-leakage multi-threshold CMOS circuits," in VLSI SoC: Forward-Looking Trends in IC and System Design, J. L. Ayala, D. A. Atienza, and R. Reis, Eds. New York: Springer-Verlag, 2012.
Index Terms
Keywords