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A Novel VLSI Architecture of Multiplier on Radix - 4 using Redundant Binary Technique
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 103 - Number 2 |
| Year of Publication: 2014 |
| Authors: L. Sriharish, M. Kamaraju |
10.5120/18046-8940
|
L. Sriharish, M. Kamaraju . A Novel VLSI Architecture of Multiplier on Radix - 4 using Redundant Binary Technique. International Journal of Computer Applications. 103, 2 ( October 2014), 23-28. DOI=10.5120/18046-8940
Abstract
The work mainly deals with in improving multiplication process by using Redundant Binary Technique. By implementing the existing method of Multiplication and Accumulation structure in Real time applications, occurs some difficulties like some hard multiples, and getting partial products in multiplication stage, it was not useful for higher radix values. The covalent redundant binary booth encoding algorithm overcomes the hard multiple generation problem and it reduces the partial products. The proposed algorithm dumped into the Booth encoding partial product generation stage. In this stage first step is to change the normal binary to redundant binary to make simple to avoid hard multiples. The partial products also reduce in the same stage. The method is implemented in the Fast Fourier Transform, Digital signal processors, and in Arithmetic logic unit. Finally the output results acquired for this method is number of gates are reduced and partial products are reduced up to 32 for 128 bit processor.
References
- Young-HO Seo, Dong-Wook Kim, "A VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm", IEEE, VLSI Systems, Vol. 18, No. 2, FEB 2010.
- H. Chang, "A power-delay efficient hybrid carry-look ahead/ array-select based redundant binary to two's complement converter, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 2, pp. 336–346, Feb. 2008.
- Kuan-Hung Chen and Yuan-Sun Chu, "A Low-Power Multiplier With the Spurious Power Suppression Technique" IEEE VLSI SYSTEMS, Vol. 15. NO. 7, July 2007.
- J. -Y. Kang and J. -L. Gaudiot, "A simple high-speed multiplier design," IEEE Trans. Comput. , vol. 55, no. 10, pp. 1253–1258, Oct. 2006
- C. Shi, W. Wang, L. Zhou, L. Gao, P. Liu, and Q. Yao, "32B RISC/DSP media processor: MediaDSP3201," SPIE Embedded Processors for Multimedia and Communications II, vol. 5683, pp. 43–52, Mar. 2005.
- Y. He, C. H. Chang, J. Gu, and H. A. H. Fahmy, "A novel covalent redundant binary Booth encoder," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS'2005), Kobe, Japan, May 2005, vol. 1, pp. 69–72.
- Y. Kim, B. -S. Song, J. Grosspietsch, and S. F. Gillig, "A carry-free 54b b multiplier using equivalent bit conversion algorithm" IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1538–1545, Oct. 2001. Y. He and C.
- B. Parhami, Computer Arithmetic Algorithms and Hardware Designs. New York: Oxford Univ. Press, 2000.
- V. Kantabutra, "A recursive carry-lookahead/carry-select hybrid adder," IEEE Trans. Comput. , vol. 42, no. 12, pp. 1495–1499, Dec. 1993. B. Parhami, Computer Arithmetic Algorithms and Hardware Designs New York: Oxford Univ. Press, 2000.
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