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Analysis of Sub Threshold to above Threshold Leakage Reduction Technique for CMOS At 65nm
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 103 - Number 17 |
| Year of Publication: 2014 |
| Authors: Shanky Goyal |
10.5120/18292-9021
|
Shanky Goyal . Analysis of Sub Threshold to above Threshold Leakage Reduction Technique for CMOS At 65nm. International Journal of Computer Applications. 103, 17 ( October 2014), 9-12. DOI=10.5120/18292-9021
Abstract
In this paper, a dual supply level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using high voltage CMOS technique. High voltage CMOS is an effective circuit level technique that improves the performance and design by utilizing high threshold voltage. In this minimum input voltage attainable while maintaining robust operation is found to be around 180mV, at maximum frequency of 1MHz. The level shifter employs an enable/disable feature, which allowing for power saving when the level shifter is not in use. Power dissipation has become an overriding concern for VLSI circuit designers. Proposed level shifter is compared with the previous work for different values of the supply voltage and when implemented on a 65nm CMOS technology, node capable of converting subthreshold voltage signals to above threshold voltage signals. . All these simulation results are based on 65nm CMOS technology and simulated in cadence tool.
References
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