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Performance Analysis of Full Adder Circuit using Improved Feed through Logic
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 101 - Number 7 |
| Year of Publication: 2014 |
| Authors: Sandeep Sangwan, Jyoti Kedia |
10.5120/17700-8678
|
Sandeep Sangwan, Jyoti Kedia . Performance Analysis of Full Adder Circuit using Improved Feed through Logic. International Journal of Computer Applications. 101, 7 ( September 2014), 27-30. DOI=10.5120/17700-8678
Abstract
In this paper performance analysis of full adder circuit has been carried out using improved feedthrough logic design technique which is a novel design technique. This technique is an improvement over already existing FTL. The circuit has been designed using existing high speed feedthrough logic and improved feedthrough logic in both 90nm and 180nm technology using cadence tools and a comparison has been done for power and delay. full adder circuit using improved FTL dissipates 37. 9% less than full adder using high speed FTL but delay is increased by 15. 13% but the overall power delay product is reduced by 28. 5%.
References
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- SauvagyaRanjanSahoo, Kamala KantaMahapatra," Performance Analysis of Modified Feedthrough Logic for Low Power and High Speed", IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012.
- SauvagyaRanjanSahoo , Kamala KantaMahapatra," An Improved Feedthrough Logic for Low Power Circuit Design", (1st Int'l Conf. on Recent Advances in Information Technology(RAIT-2012 ).
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