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Performance Analysis of Full Adder Circuit using Improved Feed through Logic

by Sandeep Sangwan, Jyoti Kedia
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 101 - Number 7
Year of Publication: 2014
Authors: Sandeep Sangwan, Jyoti Kedia
10.5120/17700-8678

Sandeep Sangwan, Jyoti Kedia . Performance Analysis of Full Adder Circuit using Improved Feed through Logic. International Journal of Computer Applications. 101, 7 ( September 2014), 27-30. DOI=10.5120/17700-8678

@article{ 10.5120/17700-8678,
author = { Sandeep Sangwan, Jyoti Kedia },
title = { Performance Analysis of Full Adder Circuit using Improved Feed through Logic },
journal = { International Journal of Computer Applications },
issue_date = { September 2014 },
volume = { 101 },
number = { 7 },
month = { September },
year = { 2014 },
issn = { 0975-8887 },
pages = { 27-30 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume101/number7/17700-8678/ },
doi = { 10.5120/17700-8678 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:31:03.861240+05:30
%A Sandeep Sangwan
%A Jyoti Kedia
%T Performance Analysis of Full Adder Circuit using Improved Feed through Logic
%J International Journal of Computer Applications
%@ 0975-8887
%V 101
%N 7
%P 27-30
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper performance analysis of full adder circuit has been carried out using improved feedthrough logic design technique which is a novel design technique. This technique is an improvement over already existing FTL. The circuit has been designed using existing high speed feedthrough logic and improved feedthrough logic in both 90nm and 180nm technology using cadence tools and a comparison has been done for power and delay. full adder circuit using improved FTL dissipates 37. 9% less than full adder using high speed FTL but delay is increased by 15. 13% but the overall power delay product is reduced by 28. 5%.

References
  1. S. M. Kang, Y. Leblebici, 'CMOS Digital Integrated Circuits: Analysis & Design', (TATA McGraw- Hill Publication, 3e, 2003).
  2. J. M. Rabaey, A. Chandrakasan, B. Nikolic, 'Digital Integrated Circuits: A Design perspective' (2e Prentice-Hall, Upper saddle River, NJ, 2002).
  3. Neil H. E. Weste, David Harris and Ayan Banerjee, "CMOS VLSI Design, A circuits and systemperspective", (3rd Edition, Pearson Education, 2005).
  4. V. Navarro-Botello, J. A. Montiel-Nelson, and S. Nooshabadi, "Analysis of high performance fast feedthrough logic families in CMOS," (IEEE Trans. Cir. & syst. II, vol. 54, no. 6, Jun. 2007, pp. 489-493).
  5. SauvagyaRanjanSahoo, Kamala KantaMahapatra," Performance Analysis of Modified Feedthrough Logic for Low Power and High Speed", IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012.
  6. SauvagyaRanjanSahoo , Kamala KantaMahapatra," An Improved Feedthrough Logic for Low Power Circuit Design", (1st Int'l Conf. on Recent Advances in Information Technology(RAIT-2012 ).
Index Terms

Computer Science
Information Sciences

Keywords

Feedthrough logic high performance logic design techniques

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