CFP last date
20 December 2024
Call for Paper
January Edition
IJCA solicits high quality original research papers for the upcoming January edition of the journal. The last date of research paper submission is 20 December 2024

Submit your paper
Know more
The week's pick
Responsive image
Improved Shuffled Frog Leaping Algorithm with Self-Adaptive Shuffling for Fuzzy Logic PD+G Controller Optimization in Robotic Manipulators

Duc Hoang Nguyen
Random Articles
Reseach Article

Low Power Blind Adaptive Equalizer with Word Length Optimization Algorithm

by N. Alivelu Manga, M. Madhavi Latha
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 100 - Number 17
Year of Publication: 2014
Authors: N. Alivelu Manga, M. Madhavi Latha
10.5120/17621-8388

N. Alivelu Manga, M. Madhavi Latha . Low Power Blind Adaptive Equalizer with Word Length Optimization Algorithm. International Journal of Computer Applications. 100, 17 ( August 2014), 55-62. DOI=10.5120/17621-8388

@article{ 10.5120/17621-8388,
author = { N. Alivelu Manga, M. Madhavi Latha },
title = { Low Power Blind Adaptive Equalizer with Word Length Optimization Algorithm },
journal = { International Journal of Computer Applications },
issue_date = { August 2014 },
volume = { 100 },
number = { 17 },
month = { August },
year = { 2014 },
issn = { 0975-8887 },
pages = { 55-62 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume100/number17/17621-8388/ },
doi = { 10.5120/17621-8388 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:30:15.380119+05:30
%A N. Alivelu Manga
%A M. Madhavi Latha
%T Low Power Blind Adaptive Equalizer with Word Length Optimization Algorithm
%J International Journal of Computer Applications
%@ 0975-8887
%V 100
%N 17
%P 55-62
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Low power VLSI is a promising area for developing advanced wireless communication systems. The optimum word length selection for each signal in algorithm is crucial for low power design. This paper proposes a scheme for Word Length Optimization (WLO) using system level parameters such as dynamic range and SNR. The Blind Adaptive Equalizer for channel equalization is optimized with the proposed technique for fixed point implementation in VHDL. Simulation is carried out in MATLAB and also VHDL. Considering IEEE 802. 16 wireless broadband network and DSL cable modem standards, the results are validated for Energy per Symbol to Noise density (Es/No) values 8 dB and 12 dB. Power saving up to 34% is observed for Xilinx's Virtex-6 FPGAs, in comparison with conventional implementation. The result shows promising direction of optimization with good scope of automation for low power wireless applications. The suitability of adopted WLO scheme in the context of High Level Synthesis (HLS) is discussed.

References
  1. David Maliniak, "Designing For Low Power? Get Started At System Level", Electronic Design, Feb 2010
  2. N. Alivelu Manga; M. Madhavi Latha, "An optimum ADC output word length selection for low power communication architectures," Advances in Computing, Communications and Informatics (ICACCI), 2013 International Conference on , vol. , no. , pp. 569,574, 22-25 Aug. 2013, doi: 10. 1109/ ICACCI. 2013. 6637235.
  3. Peiyi Zhao, "Low power design of vlsi circuits and systems", IEEE 8th International Conference on ASIC, 2009. (ASICON '09), pp: 17-20
  4. Satyam Dwivedi, Bharadwaj Amrutur and Navakanta Bhat, "Power Scalable Radio Receiver Design Based on Signal and interference condition", Journal Low Power Electron. Appl. 2012, 2,242-264; doi:10. 3390 / jlpea2040242, ISSN2079-9268
  5. Nikita Patel, Satyajit Anand and P P Bhattacharya. Article: Design of Low Power Wake-up Receiver for Wireless Sensor Network. International Journal of Computer Applications 90(10):20-25, March 2014. Published by Foundation of Computer Science, New York, USA.
  6. Jameel Hussein, Matt Klein, and Michael Hart, "Lowering Power at 28nm with Xilinx 7Series FPGAs", White paper, WP389 (v1. 1. 1) February 17, 2012 available at www. xilinx. com
  7. Moni, D. J. ; Sophia, P. E. , "Design of low power and high speed conFigurable booth multiplier," Electronics Computer Technology (ICECT), 2011 3rd International Conference on , vol. 6, no. , pp. 338,342, 8-10 April 2011, IEEE, doi: 10. 1109/ICECTECH. 2011. 5942111
  8. Sarbishei, O. ; Radecka, K. ; Zilic, Z. , "Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol. 31, no. 3, pp. 343,355, March 2012, doi: 10. 1109/TCAD. 2011. 2170988
  9. Caffarena, G. ; Carreras, C. ; Lopez, J. A. ; Fernandez, A. , "Fast fixed-point optimization of DSP algorithms," VLSI System on Chip Conference (VLSI-SoC), 2010 18th IEEE/IFIP , vol. , no. , pp. 195,200, 27-29 Sept. 2010, doi: 10. 1109/VLSISOC. 2010. 5642659
  10. Ozdil, O. ; Ispir, M. ; Onat, E. ; Yildirim, A. , "Automated fixed-point precision optimization," Signal Processing and Communications Applications Conference (SIU), 2012 20th , vol. , no. , pp. 1,4, 18-20 April 2012, doi: 10. 1109/SIU. 2012. 6204532
  11. Ramakrishnan, S. ; Balakrishnan, J. ; Ramasubramanian, K. , "Exploiting signal and noise statistics for fixed point FFT design optimization in OFDM systems," Communications (NCC), 2010 National Conference on , vol. , no. , pp. 1,5, 29-31 Jan. 2010, doi: 10. 1109/NCC. 2010. 5430229
  12. H. -N. Nguyen, D. Menard and O. Sentieys, "Novel algorithms for word length optimization", European Association for Signal Processing (EURASIP), 2011 - ISSN 2076-1465
  13. Gabriel Caffarena Fernández, Combined word length allocation and high level synthesis of digital signal processing circuits, Ph. D. Thesis 2008, GABRIEL CAFFARENA FERNÁNDEZ , INGENIERO DE TELECOMUNICACIÓN.
  14. Constantinides, G. A. , "Perturbation analysis for word-length optimization," Field-Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEE Symposium on , vol. , no. , pp. 81,90, 9-11 April 2003 doi: 10. 1109/FPGA. 2003. 1227244
  15. Tor M. Aamodt and Paul Chow, "Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy", Article No. 26, ACM Transactions on Embedded Computing Systems (TECS), Volume 7 Issue 3, April 2008, ISSN: 1539-9087 EISSN: 1558-3465 doi>10. 1145/ 1347375. 1347379
  16. Sedano, E. ; Lopez, J. A. ; Carreras, C. , "Acceleration of Monte-Carlo simulation-based quantization of DSP systems," Systems, Signals and Image Processing (IWSSIP), 2012 19th International Conference on , vol. , no. , pp. 189,192, 11-13 April 2012
  17. Yu Pang; Sarbishei, O. ; Radecka, K. ; Zilic, Z. , "Challenges in verifying and optimizing fixed-point arithmetic-intensive designs," Automation Quality and Testing Robotics (AQTR), 2010 IEEE International Conference on , vol. 2, no. , pp. 1,6, 28-30 May 2010, doi: 10. 1109/AQTR. 2010. 5520840
  18. Schmuland, T. E. ; Jamali, M. M. ; Longbrake, M. B. ; Buxa, P. E. , "Optimize hardware with fixed-point variable length phase factors," New Circuits and Systems Conference (NEWCAS), 2012 IEEE 10th International , vol. , no. , pp. 113,116, 17-20 June 2012, doi: 10. 1109/NEWCAS. 2012. 6328969
  19. Walt Kester, "Taking the Mystery out of the Infamous Formula, "SNR = 6. 02N + 1. 76dB," and Why You Should Care", Analog Devices Tutorial, MT-001 Rev. A, 10/08, WK.
  20. Amin Mohamed Nassar and Waleed El Nahal, Blind Equalization Technique for Cross Correlation Constant Modulus Algorithm (CC-CMA), ACM WSEAS Transactions on Signal Processing archive Volume 6 Issue 2, April 2010 , Pages 23-32, ISSN:1790-5022
  21. George Constantinides, Peter Y. K. Cheung and Wayne Luk, "Synthesis and Optimization of DSP Algorithms", Springer, 2004, ISBN 1402079303, 9781402079306.
  22. John R. Barry, Edward A. Lee and David G. Messerschmitt, Digital Communication , 3rd Edition, ISBN-13: 978-0792375487, Springer, P 184 – 194,
  23. Darcy Poulin (SiGe Semiconductor), Paul Piggin (Cygnus Communications), Ran Yaniv (Alvarion), Dov Andelman (Intel) "Correction to Rx SNR, Rx sensitivity, and Tx Relative Constellation Error for broad band wireless networks", http://ieee802. org/16.
  24. DOCSIS DSL reports – Acceptable cable modem signal levels, available at http://www. dslreports. com/
Index Terms

Computer Science
Information Sciences

Keywords

WLO VLSI Equalization HLS FPGA SNR Accuracy Dynamic Range

Powered by PhDFocusTM