The week's pick
Reseach Article
Modified Multiply and Accumulate Unit with Hybrid Encoded Reduced Transition Activity Technique Equipped Multiplier and Low Power 0.13µm Adder for Image Processing Applications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 1 - Number 9 |
| Year of Publication: 2010 |
| Authors: S.Saravanan, M.Madheswaran |
10.5120/198-337
|
S.Saravanan, M.Madheswaran . Modified Multiply and Accumulate Unit with Hybrid Encoded Reduced Transition Activity Technique Equipped Multiplier and Low Power 0.13µm Adder for Image Processing Applications. International Journal of Computer Applications. 1, 9 ( February 2010), 61-66. DOI=10.5120/198-337
Abstract
This paper explores the design approach of a low power high performance Multiply and Accumulate (MAC) unit with hybrid encoded Reduced Transition Activity Technique (RTAT) equipped multiplier and low power 0.13µm adder. Design of a low power MAC unit for image processing systems exploiting insignificant bits in pixels values and the similarity of neighboring pixels in video streams is presented in this paper. The proposed technique reduces dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. Special values of the pixels in the video streams such as zero, one, repeated values or repeated bit combinations are detected and data paths in the architecture design are disabled appropriately to eliminate unnecessary switching in arithmetic units. The hybrid encoder in the low power multiplier uses both the Booth and proposed technique. If the number of 1’s less than or equal to three the proposed encoding technique used otherwise go for Booth technique. By this proposed technique the number of partial products reduced by this reduction in switching activity also. The proposed adder cell used in the MAC block consumes less power than the other previous adder techniques. This high performance low power MAC can be used in image processing. It is observed from the device level simulation using TANNER 12.6 EDA that the proposed scheme helps to reduce operations and switching activities in the MAC unit up to 19% and saves power up to 46%.
References
- L. Benini, G. D. Micheli, A. Macii, E. Macii, M. Poncino, and R. Scarsi, “ Glitching power minimization by selective gate freezing,” IEEE Tran. Very Large Scale Integration. (VLSI) Syst., vol. 8, no. 3, pp. 287–297, June 2000.
- H. T. Bui, Y. Wang, and Y. Jiang, “Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 1, pp. 25–30, Jan 2002.
- A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design. Norwell, MA: Kluwer, 1995.
- C.H. Chang, J. Gu, M. Zhang, “A review of 0.18-µm full adder performances for tree structured arithmetic circuits,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst.vol. 13, no.6, pp. 686–695, June 2005.
- K.H.Chen and Y.S.Chu, “A low power multiplier with spurious power suppression technique, ” IEEE Trans.Very Large Scale Integr. (VLSI) Syst.vol. 15, no.7, pp. 846–850, July 2007.
- O. Chen, R. Sheen, and S. Wang, “A low power adder operating on effective dynamic data ranges,” IEEE Transaction. Very Large Scale Integration. (VLSI) Syst., vol. 10, no.4, pp.435–453, Aug. 2002.
- O. Chen, S. Wang, and Y. W. Wu, “Minimization of switching activities of partial products for designing low-power multipliers,” IEEE Transaction. Very Large Scale Integration. (VLSI) Syst., vol. 11, no.3, pp. 418–433, Jun. 2003.
- J. Choi, J. Jeon and K. Choi, “Power minimization of functional units by partially guarded computation,” in Proc.IEEE International Symposium Low Power Electron. Devices, pp. 131–136, 2000.
- K. Gandhi, and N. Mahaptra, “Dynamically exploiting frequent operand values for energy efficiency in integer functional units,” proceeding. 18th Intl. Conf. on VLSI Design, pp. 570-575, 2005.
- S. Henzler, G. Georgakos, J. Berthold, and D.Schmitt- Landsiedel, “Fast power-efficient circuit-block switch off scheme,” Electronics Letter. vol. 40, no. 2, pp. 103–104, Jan. 2004.
- Z.Huang and M. D. Ercegovac, “On signal gating schemes for low power adders,” in Proc. 35th Asilomar Conference. Signal, Systems. Computer. 2003.
- Z. Huang and M. D. Ercegovac, “High performance low power left-to-right array multiplier design,” IEEE Transaction on Computer., vol. 54, no. 3, pp. 272-283, March 2005.
- U.Ko, P.Balsara and W.Lee, “Low-power design techniques for high-performance CMOS adders,” IEEE Transaction on Very Large Scale Integration (VLSI) System. volume.3, no.2, pp.327-333, June 1995.
- A. Shams, T. Darwish and M. Bayoumi, “Performance analysis of low power 1-bit CMOS full adder cells,” IEEE Trans. Very Large Scale Integr(VLSI) Syst., vol. 10, no. 1, pp. 20–29, Feb. 2002.
- P.J.Song and G.De Micheli, “Circuit and architecture trade-offs for high-speed multiplication,” IEEE journal on Solid-State Circuits, Vol.26,no.9, pp.1184-1198, Sep.1991.
- M. Vesterbacka, “A 14-transistor CMOS full adder with full voltage swing nodes,” in Proc. IEEE Workshop Signal Processing Systems, pp. 713–722, Oct. 1999.
- M. C. Wen, S. J. Wang and Y. N. Lin, “Low-power parallel multiplier with column by passing,” Electron. Lett. vol. 41, no. 12, pp. 581–583, May 2005.
- N.Weste and K. Eshraghian, Principles of CMOSVLSI Design, A System.Perspective. Reading, MA: Addison-Wesley, 1993.
- N. Zhuang and H. Hu, “A new design of the CMOS full adder,” IEEE JSolid-State Circuits, vol. 27, no. 5, pp. 840–844, May 1992
Index Terms
Keywords