The week's pick
Reseach Article
NANO Scale SOI MOSFET Structures and Study of Performance Factors
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 1 - Number 28 |
| Year of Publication: 2010 |
| Authors: Prakash Baviskar, Prasad Vinchurkar, Sanjeev Jain |
10.5120/513-830
|
Prakash Baviskar, Prasad Vinchurkar, Sanjeev Jain . NANO Scale SOI MOSFET Structures and Study of Performance Factors. International Journal of Computer Applications. 1, 28 ( February 2010), 36-41. DOI=10.5120/513-830
Abstract
This paper proposes a study related with the downscaling trend in CMOS devices. Some of the structural variants of the MOSFET have been explored and the key performance factors as gate tunneling current, transconductance and output conductance are discussed. The impact of energy quantization on gate tunneling current is studied for double-gate and ultra thin body MOSFETS. Reduced vertical electric field and quantum confinement in the channel of these thin-body devices causes a decrease in gate leakage. Very high transconductance, approaching the ballistic limit, can be achieved provided that technological improvements further increase the electron mobility in the silicon film. The output conductance and Early voltage are severely affected by length scaling as channel length-modulation (CLM) and drain-induced barrier lowering (DIBL) effects become more important, but they are acceptable for channel lengths above 15 nm.
References
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