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8-Bit Sub Threshold Ripple Carry Adders in 32nm CMOS Technology for Wireless Sensor nodes.

by R. Savari Rani, C.Christober Asir Rajan, Arini V.H
journal cover thumbnail
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 1 - Number 23
Year of Publication: 2010
Authors: R. Savari Rani, C.Christober Asir Rajan, Arini V.H
10.5120/529-692

R. Savari Rani, C.Christober Asir Rajan, Arini V.H . 8-Bit Sub Threshold Ripple Carry Adders in 32nm CMOS Technology for Wireless Sensor nodes.. International Journal of Computer Applications. 1, 23 ( February 2010), 89-95. DOI=10.5120/529-692

@article{ 10.5120/529-692,
author = { R. Savari Rani, C.Christober Asir Rajan, Arini V.H },
title = { 8-Bit Sub Threshold Ripple Carry Adders in 32nm CMOS Technology for Wireless Sensor nodes. },
journal = { International Journal of Computer Applications },
issue_date = { February 2010 },
volume = { 1 },
number = { 23 },
month = { February },
year = { 2010 },
issn = { 0975-8887 },
pages = { 89-95 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume1/number23/529-692/ },
doi = { 10.5120/529-692 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T19:48:08.864116+05:30
%A R. Savari Rani
%A C.Christober Asir Rajan
%A Arini V.H
%T 8-Bit Sub Threshold Ripple Carry Adders in 32nm CMOS Technology for Wireless Sensor nodes.
%J International Journal of Computer Applications
%@ 0975-8887
%V 1
%N 23
%P 89-95
%D 2010
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Subthreshold design has been proposed in the literature as an effective technique for designing signal processing circuits needed in wireless sensor nodes powered by sources with limited energy. The full adder cell forms the basic building block of majority of these signal processing circuits. In this paper, 8-Bit subthreshold Ripple Carry Adders (RCAs) for wireless sensor nodes optimized for ultra low power operation are proposed. Major contribution of this work is conversion of BSIM4, Predictive Technology Model (32nm) to EKV model ( charge based model). The 8-bit RCAs are simulated with HSPICE (Level =55) using the 32nm CMOS technology at supply voltages ranging from 0.25V to 0.4V. Various metrics such as delay, average power and power delay product (PDP) are simulated and reported for effective twelve different topologies. The circuit designers can choose the full adder topology and the supply voltage that is suitable for their applications. Usage of EKV models results in 11% reduction in power than that of using BSIM models for the adder cell “CB” with supply voltage of 0.2V.

References
  1. R. Pedram, M. Pedram, Low Power Design Methodologies, Kluwer, Norwell, MA, 1996.
  2. Enz, Christian C., Vittoz, Eric A, Charge-Based MOS Transistor Modeling: The EKV Model for Low-Power and RF IC Design, Wiley, 2008.
  3. A.M. Shams, T.K. Darwish, M.A. Bayoumi, “Performance analysis of low-power 1-bit CMOS full adder cells,” IEEE Transactions on VLSI Systems, Vol. 10, pp. 20–29, Jan. 2002.
  4. V. Moalemi, A. Afzali Koosha, “Subthreshold 1-Bit Full Adder Cells in sub-100 nm Technologies “, Proc. of the IEEE Computer Society Annual Symposium on VLSI, pp. 514-515, 2007.
  5. http://legwww.epfl.ch/ekv/
  6. http://www.eas.asu.edu/~ptm/
  7. A. M. Shams and M. A Bayoumi, “A Framework for Fair Performance Evaluation of 1-bit Full Adder Cells,” 42nd Midwest Symposium on Circuits and Systems, MWSCAS’99, Las Cruces, NM, USA, Aug. 8– 11, 1999.
  8. Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello, “New Performance/Power/Area Efficient, Reliable Full Adder Design,” GLSVLSI’09, pp.493-498, May 10–12, 2009, Boston, Massachusetts, USA.
  9. M. Hemstead, N. Tripathi, P. Mauro, G. Y. Wei, and D. Brooks, “An ultra-low power system architecture for sensor network applications,” ISCA, pp. 208-219, 2005.
Index Terms

Computer Science
Information Sciences

Keywords

CMOS Wireless Sensor nodes

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