In a clause of combinational circuits, the throughput can be increased, without (wave) pipelining, by introducing data dependent delay feature thus avoiding the worst case delay. That is, in circuits like multipliers and adders which are the basic building blocks of any DSP system; the processing delay can be varied according to the magnitude of the input data. This makes the circuit asynchronous and necessitates a controller to arbitrate the data. Systems like FIR filters, where a series of combinational multipliers are used, can be asynchronously pipelined with a controller regulating the data between stages. With this system level pipelining, speed of circuit level pipelining can be achieved provided the data are of low magnitude. In this paper, two controller architectures are presented to regulate the data flow between asynchronously pipelined stages. Firstly, as a stepping stone, Altera’s soft-core NIOS processor [1] is used and secondly, an exclusive asynchronous controller is designed using HDL. These controllers are designed to suit asynchronous implementation in conventional FPGAs, to effectively handle repeated data and to perform self-test. These controllers issue the control signals to the various dual edge triggered pipelined registers to process the data in both the edges for further improving speed. In the HDL version of the controller, programmable delays are generated by a ‘logic locked’ high frequency counter without using delay elements. To verify the efficacy of these controllers 2 tap FIR filter is implemented using Braun array multipliers and adders. Thus, this approach consumes lower power and achieves data dependent throughput and also avoids the need for global clock signals and skew problems.

Asynchronous FPGA Low power Asynchronous Controller Data Dependent Delay